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SCIENTIA SINICA Informationis, Volume 50 , Issue 2 : 289-302(2020) https://doi.org/10.1360/N112018-00247

A memristor-CMOS-based general-logic circuit and its applications

More info
  • ReceivedSep 10, 2018
  • AcceptedMar 21, 2019
  • PublishedFeb 12, 2020

Abstract


Funded by

国家重点研发计划(2018YFB1306600)

国家自然科学基金(61571372,61672436,61601376)

重庆市基础科学与前沿技术研究专项重点项目(cstc2017jcyjBX0050,cstc2016jcyjA0547)

中央高校基本科研业务费(XDJK2016A001,XDJK2017A005)

西南大学博士基金(SWU116005)


References

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  • Figure 1

    Proposed general logic circuits

  • Figure 2

    (Color online) The simulation result of proposed general logic circuit. (a) $V_{a}=~V_{L}=~``0",~V_{b}=~V_{L}=~``0"$; protectłinebreak (b) $V_{a}=~V_{L}=~``0",~V_{b}=~V_{H}=~``1"$; (c) $V_{a}=~V_{H}=~``1",~V_{b}=~V_{L}=~``0"$; (d) $V_{a}=~V_{H}=~``1",~V_{b}=~V_{H}=~``1"$

  • Figure 3

    Proposed memristor-CMOS hybrid full adder

  • Figure 4

    (Color online) The simulation results of memristor-CMOS hybrid full adder when $V_{\rm~cin}=V_{L}$. (a) $V_{A}=V_{L}$, $V_{B}=V_{L}$; (b) $V_{A}=V_{L}$, $V_{B}=V_{H}$; (c) $V_{A}=V_{H}$, $V_{B}=V_{L}$; (d) $V_{A}=V_{H}$, $V_{B}=V_{H}$

  • Figure 5

    (Color online) The simulation results of memristor-CMOS hybrid full adder when $V_{\rm~cin}=V_{L}$. (a) $V_{A}=V_{L}$, $V_{B}=V_{L}$; (b) $V_{A}=V_{L}$, $V_{B}=V_{H}$; (c) $V_{A}=V_{H}$, $V_{B}=V_{L}$; (d) $V_{A}=V_{H}$, $V_{B}=V_{H}$

  • Figure 6

    Proposed encryption cell based general logic circuit

  • Figure 7

    Proposed encryption circuit for binary image

  • Figure 8

    (Color online) Original imagematrix and key matrix. (a) Numeric “5" matrix; (b) key matrix

  • Figure 9

    (Color online) Encryption and decryption process

  • Figure 10

    Original Lena image and key

  • Figure 11

    Encryption and decryption process for Lena image

  • Table 1   Implementation process of proposed general logic circuit
    Logic Truth table Input Node voltage Output
    $a$ $b$
    AND 0 0$\to~$0 $V_{L}$ $V_{L}$ $X_1$$\to$$V_{L}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{L}$$\to$Logic“0”
    0 1$\to$0 $V_{L}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{L}$$\to$Logic“0”
    1 0$\to$0 $V_{H}$ $V_{L}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{L}$$\to$Logic“0”
    1 1$\to$1 $V_{H}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{H}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{H}$$\to$Logic“1”
    OR 0 0$\to$0 $V_{L}$ $V_{L}$ $X_1$$\to$$V_{L}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{L}$$\to$Logic“0”
    0 1$\to$1 $V_{L}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{H}$$\to$Logic“1”
    1 0$\to$1 $V_{H}$ $V_{L}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{H}$$\to$Logic“1”
    1 1$\to$1 $V_{H}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{H}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{H}$$\to$Logic“1”
    XOR 0 0$\to$0 $V_{L}$ $V_{L}$ $X_1$$\to$$V_{L}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{L}$$\to$Logic“0”
    0 1$\to$1 $V_{L}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{H}$$\to$Logic“1”
    1 0$\to$1 $V_{H}$ $V_{L}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{H}$$\to$Logic“1”
    1 1$\to$0 $V_{H}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{H}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{L}$$\to$Logic“0”
    XNOR 0 0$\to$1 $V_{L}$ $V_{L}$ $X_1$$\to$$V_{L}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{H}$$\to$Logic“1”
    0 1$\to$0 $V_{L}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{L}$, $X_3$$\to$$V_{H}$, $X_4$$\to$$V_{L}$ $V_{L}$$\to$Logic“0”
    1 0$\to$0 $V_{H}$ $V_{L}$ $X_1\to~V_{H}$, $X_2\to~V_{L}$, $X_3\to~V_{H}$, $X_4\to~V_{L}$ $V_{L}\to$Logic“0”
    1 1$\to$1 $V_{H}$ $V_{H}$ $X_1$$\to$$V_{H}$, $X_2$$\to$$V_{H}$, $X_3$$\to$$V_{L}$, $X_4$$\to$$V_{H}$ $V_{H}$$\to$Logic“1”
  • Table 2   Several logic circuits' performance for implementation of AND-OR-XOR-XNOR logic
    Logic circuits Components Generalized Power estimation Circuit design constraints Cascading
    Proposed general 4 memristors Excellent 1.592 mW Low Excellent
    logic circuit 4 MOSFETs
    13 memristors
    MAD Gates 13 resistors Normal 4.306 mW High Normal
    7 switches
    MRL 16 memristors Normal 6.312 mW Low Excellent
    10 MOSFETs
    IMPLY 18 memristors Normal 12.490 mW High Normal
    4 resistors
    Hybrid CMOS 8 memristors Good 3.183 mW Low Excellent
    4 MOSFETs
  • Table 3   The truth table of full adder
    Carry voltage Input Output
    $V_{A}$ $V_{B}$
    $V_{\rm~cin}~\to~V_{L}$ $V_{L}$ $V_{L}$ $V_{\rm~sum}$ $\to$ $V_{L}$, $V_{\rm~cout}$ $\to$ $V_{L}$
    $V_{L}$ $V_{H}$ $V_{\rm~sum}$ $\to$ $V_{H}$, $V_{\rm~cout}$ $\to$ $V_{L}$
    $V_{H}$ $V_{L}$ $V_{\rm~sum}$ $\to$ $V_{H}$, $V_{\rm~cout}$ $\to$ $V_{L}$
    $V_{H}$ $V_{H}$ $V_{\rm~sum}$ $\to$ $V_{L}$, $V_{\rm~cout}$ $\to$ $V_{H}$
    $V_{\rm~cin}$ $\to$ $V_{H}$ $V_{L}$ $V_{L}$ $V_{\rm~sum}$ $\to$ $V_{H}$, $V_{\rm~cout}$ $\to$ $V_{L}$
    $V_{L}$ $V_{H}$ $V_{\rm~sum}$ $\to$ $V_{L}$, $V_{\rm~cout}$ $\to$ $V_{H}$
    $V_{H}$ $V_{L}$ $V_{\rm~sum}$ $\to$ $V_{L}$, $V_{\rm~cout}$ $\to$ $V_{H}$
    $V_{H}$ $V_{H}$ $V_{\rm~sum}$ $\to$ $V_{H}$, $V_{\rm~cout}$ $\to$ $V_{H}$
  • Table 4   Comparison of the components required by the proposed circuits and prior work for $N$-bit adder
    MAD Gates MRL IMPLY Proposed general logic circuit
    Components $8N$ memristors $18N$ memristors $7N+1$ memristors $4N~$ memristors
    $2N+3$ drivers $3N$ drivers $7N$ drivers $2N+1$ drivers
    $9N$ resistors $4N$ MOSFETs $~N$ resistors $8N$ MOSFETs
    $14N$ switches $8N-1$ switches