上海市浦江人才(16PJ1407600)
中国博士后科学基金(2017M610230)
国家自然科学基金重点项目(61332009)
国家自然科学基金面上项目(61775139)
上海市自然科学基金(15ZR1428600)
计算机体系结构国家重点实验室开放课题(CARCH201807)
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Figure 1
Structure of heterogeneous memory system. (a) Flat memory architecture; (b) hierarchical memory architecture
Figure 2
(Color online) Structure of two-way Hash chain list
Figure 3
Structure of HashList and entry table
Figure 4
Energy efficiency analysis model based on two-way Hash chain list page migration mechanism
Figure 5
(Color online) Normalized IPC for different size of pages (DRAM+PCM memory model). (a) THMigrator;protect łinebreak (b) MQMigrator; (c) CoinMigrator
Figure 6
(Color online) Normalized IPC for different size of pages (DRAM+STT-RAM memory model). (a) THMigrator; (b) MQMigrator; (c) CoinMigrator
Figure 7
(Color online) Normalized instruction rate for different size of pages (DRAM+PCM memory model).protect łinebreak (a) THMigrator; (b) MQMigrator; (c) CoinMigrator
Figure 8
(Color online) Normalized instruction rate for different sizes of pages (DRAM+STT-RAM memory model).protect łinebreak (a) THMigrator; (b) MQMigrator;(c) CoinMigrator
Figure 9
(Color online) Normalized IPC. (a) DRAM+PCM heterogeneous memory system; (b) DRAM+STT-RAM heterogeneous memory system
Figure 10
(Color online) Average instruction rate. (a) DRAM+PCM heterogeneous memory system; (b) DRAM+STT-RAM heterogeneous memory system
Figure 11
(Color online) DRAM cache utilization. (a) DRAM+PCM heterogeneous memory system; (b) DRAM+STT-RAM heterogeneous memory system
Figure 12
(Color online) Normalized energy efficiency. (a) DRAM+PCM heterogeneous memory system; (b) DRAM+protect łinebreak STT-RAM heterogeneous memory system
Figure 13
(Color online) Average latency of accessing memory. (a) DRAM+PCM heterogeneous memory system;protect łinebreak (b) DRAM+STT-RAM heterogeneous memory system
Figure 14
(Color online) The hit-rates of write access. (a) DRAM+PCM heterogeneous memory system; (b) DRAM+protect łinebreak STT-RAM heterogeneous memory system
Figure 15
(Color online) The normalized execute time. (a) DRAM+PCM heterogeneous memory system; (b) DRAM+protect łinebreak STT-RAM heterogeneous memory system
Figure 16
(Color online) The normalized time of migration with THMigrator mechanism
Figure 17
(Color online) The normalized time of migration with MQMigrator mechanism
Figure 18
(Color online) The normalized time of migration with CoinMigrator mechanism
| Storage/memory | Reciprocal density | Read speed | Write speed | Read power/mW | Write power/mW | Endurance |
| DRAM | $4-6{F}^{2}$ | Slow | Slow | Medium | Medium | ${10}^{16}$ |
| PCM | $4-12{F}^{2}$ | Slow | VerySlow | Medium | High | ${10}^{8}-{10}^{9}$ |
| STT-RAM | $6-50{F}^{2}$ | Fast | Slow | Low | High | $4~\times~{10}^{12}$ |
1: /*Initialize variables*/ |
2: Initialize HashList, MigratorMap, lifeTime, Threshold, etc.; |
3:Request(${\rm page}_i$); /*Request access to the $i$-th memory page*/ |
4: |
5: $ {\rm page}_i \rightarrow {\rm value} \Leftarrow {\rm page}_i \rightarrow {\rm value}+1 $; /*the value of ${\rm page}_i$ add 1*/ |
6: moveToHead(${\rm page}_i$); /*Move ${\rm page}_i$ to the head of HashList*/ |
7: |
8: setHead(${\rm page}_i$); /*Set ${\rm page}_i$ to the head of HashList*/ |
9: |
10: |
11: MigratorMap.insert(${\rm page}_i$); /*Insert ${\rm page}_i$ into MigratorMap*/ |
12: HashList.remove(${\rm page}_i$); /*Remove ${\rm page}_i$ from HashList*/ |
13: |
14: |
15: MigratorMap.remove(${\rm page}_i$); /*Remove memory pages that exceed the life time*/ |
16: |
17: InMigratorMap(${\rm page}_i$)&&!Migratored(${\rm page}_i$) |
18: startMigrator(${\rm page}_i$); /*Migrate ${\rm page}_i$ from NVM to DRAM*/ |
19: MigratorMap.remove(${\rm page}_i$); /*Remove memory pages that exceed the life time*/ |
20: |
| Memory | Read latency | Write latency | Read energy | Write energy | Read speed | Write speed |
| DRAM | 3 $\mu$s (4 KB) | 3 $\mu$s (4 KB) | 0.8 J/GB | 1 J/GB | 1.09 GB/s | 1 GB/s |
| PCM | 3 $\mu$s (4 KB) | 64 $\mu$s (4 KB) | 1.2 J/GB | 6 J/GB | 400 MB/s | 100 MB/s |
| Configuration parameter | Value |
| CPU | 2.0 GHZ + TimingSimpleCPU |
| Mempry | NVMainMemory |
| L1 cache | 32 KB instruction cache + 32 KB data cache |
| L2 cache | 256 KB instruction cache + 256 KB data cache |
| Memory structure | DRAM + PCM (1:3) |
| Bus | 64 bit |
| Operation mode | SE mode |
| Benchmarks | The number of instruction |
| bzip2 | 10000000 |
| gcc | 10000000 |
| leslie3d | 10000 |
| mcf | 10000 |
| calculix | 10000000 |
| cactusADM | 10000 |
| sjeng | 10000000 |
| hmmer | 10000000 |
| milc | 10000 |
| povray | 10000000 |
| soplex | 10000000 |
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