SCIENTIA SINICA Informationis, Volume 48 , Issue 6 : 701-712(2018) https://doi.org/10.1360/N112018-00009

## Design of communication architecture for flexible electronic system based on honeycomb

• AcceptedMar 27, 2018
• PublishedJun 6, 2018
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### References

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• Figure 1

Diagram of a flexible and stretchable electronic system

• Figure 2

(Color online) Diagram of island-bridge structure

• Figure 3

Diagram of flexible and stretchable electronic system based on network-on-chip

• Figure 4

(Color online) Diagram of the communication architecture of honeycomb network-on-chip (a) and the structure model of honeycomb network-on-chip (b)

• Figure 5

(Color online) Stress and strain distribution of the honeycomb network-on-chip when tension is 10%. (a) Overall stress distribution; (b) overall strain distribution

• Figure 6

(Color online) Stress and strain distribution of the honeycomb network-on-chip when compression is 10%.protect łinebreak (a) Overall stress distribution; (b) overall strain distribution

• Figure 7

(Color online) Stress and strain distribution of the honeycomb network-on-chip when it is bent. (a) Overall stress distribution; (b) overall strain distribution

• Figure 8

Diagram of different topologies. (a) SPIN; (b) BFT; (c) Mesh; (d) Torus; (e) Octagon; (f) Spidergon

• Figure 9

(Color online) Diagram of routing algorithm in honeycomb network-on-chip

• Figure 10

Turn model of routers. (a) Turn model of routers on odd node; (b) turn model of routers on even node

•

Algorithm 1 Routing algorithm OEXY

Require:$C$(Xc,Yc), $D$(Xd,Yd);

while (Xc,Yc) $\neq$ (Xd,Yd) do

if Xc is odd then

if Yc $>$ Yd then

Go down;

Yc = Yc $-$ 1;

else

if Xc $<$ Xd then

Turn right;

Xc = Xc $+$ 1;

else

Turn left;

Xc = Xc $-$ 1;

end if

end if

else

if Yc $<$ Yd then

Go up;

Yc = Yc $+$ 1;

else

if Xc $<$ Xd then

Turn right;

Xc = Xc $+$ 1;

else

Turn left;

Xc = Xc $-$ 1;

end if

end if

end if

end while

Output: Output port of the router.

• Table 1   Comparison of the parameters of different topologies
 Topology IPs Routers Node degree Diameter Links SPIN [12] $N$ $3N/4~(N\geqslant64)$ 4 $N/8$ $7N/2~(N\geqslant64)$ BFT [13] $N$ $N/2$ 6 $N/8$ $2N$ Mesh [14] $N$ $N$ 5 $2(\sqrt{N}-1)$ $3N-2\sqrt{N}$ Torus [15] $N$ $N$ 5 $2[\sqrt{N}/2]$ $3N$ Octagon [16] $N$ $N$ 7 $[N/4]$ $({\rm~Nmod}(8)+1)~\times~20$ Spidergon [17] $N$ $N$ 4 $[N/4]$ $5N/2$ Proposed $N$ $N$ 4 $[5\sqrt{N}/2]-3$ $5N/2$
• Table 2   Basic parameters of different topologies
 Topology IPs Routers Length of message (flits) Depth of buffer (flits) Routing algorithm SPIN [12] 16 8 32 2 NCA [18] BFT [13] 16 6 32 2 NCA [18] Mesh [14] 16 16 32 2 XY [18] Torus [15] 16 16 32 2 Adapt_XY [18] Octagon [16] 16 16 32 2 Adapt_min [18] Spidergon [17] 16 16 32 2 Adapt_min [18] Proposed 16 16 32 2 Proposed
• Table 3   Comparison of the area of different topologies
 Area ($\mu$m$^{2}$) SPIN BFT Mesh Torus Octagon Spidergon Proposed Channel 0.04 0.03 0.05 0.09 0.05 0.05 0.04 Switch 0.13 0.05 0.17 0.17 0.11 0.11 0.07 Input FIFO 0.03 0.02 0.05 0.05 0.04 0.04 0.03 Output FIFO 0.01 0.01 0.01 0.01 0.01 0.01 0.01 Total [16] 0.21 0.11 0.28 0.32 0.21 0.20 0.15
• Table 4   Comparison of the power comsumption of different topologies
 Power (mW) SPIN BFT Mesh Torus Octagon Spidergon Proposed Channel wire power 15.28 11.97 18.66 26.03 13.40 11.51 13.59 Channel clock power 0.48 0.36 0.73 1.21 0.62 0.61 0.52 Channel retiming power 0.19 0.15 0.23 0.32 0.17 0.14 0.17 Channel leakage power 0.18 0.14 0.27 0.46 0.23 0.23 0.19 Input read power 0.29 0.21 0.39 0.35 0.28 0.24 0.29 Input write power 0.29 0.21 0.39 0.35 0.28 0.24 0.29 Input leakage power 0.03 0.02 0.05 0.05 0.04 0.04 0.03 Switch power 2.04 0.78 1.82 1.66 1.02 0.84 0.86 Switch control power 0.71 0.30 0.69 0.62 0.43 0.34 0.36 Switch leakage power 0.49 0.13 0.47 0.47 0.28 0.26 0.16 Output DFF power 0.07 0.05 0.09 0.08 0.06 0.06 0.07 Output Clk power 0.18 0.12 0.30 0.30 0.25 0.24 0.20 Output control power 0.04 0.03 0.05 0.04 0.03 0.03 0.04 Total power 20.27 14.47 24.12 31.94 17.10 14.77 16.76

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