SCIENTIA SINICA Informationis, Volume 49 , Issue 3 : 342-360(2019) https://doi.org/10.1360/N112017-00200

## Threshold voltage and DIBL effect analysis and modeling for FD-SOI MOSFET with high k + SiO$_2$ gate

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• ReceivedOct 13, 2017
• AcceptedMar 28, 2018
• PublishedMar 15, 2019
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### Supplement

Appendix

$$C_{{\rm edge}}=\frac{2\varepsilon}{2\pi}{\rm ln}\frac{2\pi w}{t}=\frac{\varepsilon}{\pi}{\rm ln}\frac{2\pi w}{t}, \tag{33}$$ 式(A1)中$\varepsilon$是介电常数, $w$和$t$分别是栅的宽度和介质材料厚度.因此完整的栅电容是 $$C_{{\rm g}}^\prime=\frac{\varepsilon}{\pi}{\rm ln}\frac{2\pi w}{t}+\frac{\varepsilon}{\pi}wl, \tag{34}$$ 式中$l$是栅长度. 单位面积的栅电容是 $$C_{{\rm g}}=\frac{C_{{\rm g}}^\prime}{lw}=\varepsilon\bigg[\frac{1}{t}+\frac{1}{lw\pi}{\rm ln}\frac{2\pi w}{t}\bigg], \tag{35}$$ 上式表明单位面积的电容与沟道长度、介电常数、栅宽都有影响. par 下面用式(A3)计算不同介质的单位面积栅长电容. SiO$_2$介电常数是$\varepsilon_{{\rm~ox}}$, 栅介质电容是 $$C_{{\rm ox}}=\varepsilon_{{\rm ox}}\bigg[\frac{1}{t_{{\rm ox}}}+\frac{1}{lw\pi}{\rm ln}\frac{2\pi w}{t_{{\rm ox}}}\bigg]=C_0\bigg[1+\frac{t_{{\rm ox}}}{lw\pi}{\rm ln}\frac{2\pi w}{t_{{\rm ox}}}\bigg], \tag{36}$$ 式(A4)中$C_0=\frac{\varepsilon_{{\rm~ox}}}{t_{{\rm~ox}}}$, 是单位面积的平行板栅电容, 称作栅的本征电容. 若用等电容设计, 设高k材料介电常数是$\varepsilon_{{\rm~k}}$, 则有$t_{{\rm~g}}=\frac{\varepsilon_{{\rm~k}}}{\varepsilon_{{\rm~ox}}}t_{{\rm~ox}}$, 高k栅电容是 $$C_k=\varepsilon_{{\rm k}}\bigg[\frac{1}{t_{\rm k}}+\frac{1}{\pi lw}{\rm ln}\frac{2\pi w}{t_{\rm k}}\bigg]= C_0\bigg[1+\frac{t_{\rm ox}}{\pi lw}\frac{\varepsilon_{{\rm k}}}{\varepsilon_{{\rm ox}}}\bigg({\rm ln}\frac{2\pi w}{t_{\rm ox}}-{\rm ln}\frac{\varepsilon_{{\rm k}}}{\varepsilon_{{\rm ox}}}\bigg)\bigg]. \tag{37}$$

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• Figure 1

High k + SiO$_2$ gate FD-SOI MOSFET structure diagram

• Figure 2

Calculates the coordinate system of the high k + SiO$_2$ gate FD-SOI MOSFET

• Figure 3

$\varepsilon_{{\rm~k}}=22$ high k dielectric high k + SiO$_2$ gate FD-SOI MOSFET front gate surface potential with the gate voltage changes

• Figure 4

High k + SiO$_2$ gate FD-SOI MOSFET front gate surface potential along the channel length distribution.protect łinebreak (a) $\varepsilon_{{\rm~k}}=7.5$ medium; (b) $\varepsilon_{{\rm~k}}=22$ medium

• Figure 5

High k and high k + SiO$_2$ gate FD-SOI MOSFET threshold voltage algorithm flow chart

• Figure 6

(a) High k gate, high k + SiO$_2$ gate and SiO$_2$ gate FD-SOI MOSFET threshold voltage and channel length relationship; (b) the relationship between threshold voltage and channel length of high k + SiO$_2$ gate FD-SOI MOSFET with different media

• Figure 7

FD-SOI MOSFET threshold voltage and the device's physical structure and material parameters of the relationship. (a) High k gate material unchanged, change the Si film doping concentration; (b) all parameters remain unchanged, only change the thickness of the Si film; (c) high k material unchanged, only change the ratio of high k layer and SiO$_2$ layer; (d) the high k material and device structure remain unchanged, changing only the back gate oxide thickness; (e) high k material and structure unchanged, plus different back gate voltage

• Figure 8

High k + SiO$_2$ gate FD-SOI MOSFET threshold voltage and dielectric constant relationship, the abscissa is the high k material dielectric constant. (a) Long channel (60 nm) situation; (b) the channel length is 20 nm short channel condition; (c) different thickness of the high k + SiO$_2$ gate, the channel length is 20 nm situation

• Figure 9

(a) The diagrammatic sketch for the leakage electric field intensity of two sides between the gate; (b) the edge effect discussed in the paper

• Figure 10

Surface potential distribution of SiO$_2$ gate, high k gate and high k + SiO$_2$ gate FD-SOI MOSFETs. protect łinebreak (a) The channel length is the surface potential $\phi_{\rm~f}(x)$ of 110 nm; (b) the channel length is 20 nm, the surface potential $\phi_{\rm~f}(x)$;protect łinebreak (c) the barrier map of (b), the unit is V

• Figure 11

20 nm channel length FD-SOI MOSFET $V_{{\rm~GS}}=0.3$ V, $V_{{\rm~GS}}$ and barrier height difference $\nabla\Phi$ diagram

• Table 1   Capacitor capacitance per unit area of SiO$_2$ gate, high k + SiO$_2$ gate and high k gate
 Channel length ($l$) 110 nm 20 nm Gate capacitance of SiO$_2$ ($C_{\rm~ox}$) (1+0.0664)$C_0$ (1+0.365)$C_0$ Gate capacitance of high k + SiO$_2$ ($C_{\rm~k+SiO_2}$) (1+0.157)$C_0$ (1+0.637)$C_0$ Gate capacitance of high k ($C_{\rm~k}$) (1+0.295)$C_0$ (1+1.623)$C_0$
• Table 2   Figure $V_{\rm~GS}=0.3$ V, 20 nm channel FD-SOI MOSFET surface potential $\phi_{\rm~f}(x)$ data
 $X$ (nm) 50 50.8 52.4 55.1 60 64.9 67.6 69.2 70 *SiO$_2~\phi_{\rm~f}(x)$ SILVACO 0.5852 0.5174 0.4577 0.4089 0.4042 0.4827 0.5854 0.6859 0.7852 Model 0.5828 0.525 0.4771 0.4332 0.4234 0.5041 0.5947 0.7221 0.7807 *High k + SiO$_2~\phi_{\rm~f}(x)$ SILVACO 0.5852 0.5213 0.4705 0.433 0.4345 0.5077 0.5979 0.6886 0.7852 Model 0.5829 0.5288 0.4885 0.4534 0.4516 0.5247 0.6037 0.6818 0.7804 *High k$~\phi_{\rm~f}(x)$ SILVACO 0.5852 0.5608 0.5305 0.5033 0.514 0.5949 0.6787 0.742 0.7852 Model 0.5824 0.5469 0.5218 0.5007 0.5076 0.5756 0.6415 0.7306 0.7785

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