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SCIENCE CHINA Information Sciences, Volume 64 , Issue 10 : 201402(2021) https://doi.org/10.1007/s11432-021-3271-8

Carbon nanotube-based CMOS transistors and integrated circuits

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  • ReceivedMar 31, 2021
  • AcceptedMay 24, 2021
  • PublishedAug 20, 2021

Abstract


Acknowledgment

This work was supported by National Key Research Development Program (Grant No. 2016YFA0201901) and Beijing Municipal Science and Technology Commission (Grant No. Z181100004418011).


References

[1] 2-YChemPhysChem 2001, 2: 482--489. Google Scholar

[2] Bardeen J, Brattain W H. The Transistor, A Semi-Conductor Triode. Phys Rev, 1948, 74: 230-231 CrossRef ADS Google Scholar

[3] Cavin R K, Lugli P, Zhirnov V V. Science and Engineering Beyond Moore's Law. Proc IEEE, 2012, 100: 1720-1749 CrossRef Google Scholar

[4] Waldrop M M. The chips are down for Moore's law. Nature, 2016, 530: 144-147 CrossRef ADS Google Scholar

[5] Avouris P, Chen J. Nanotube electronics and optoelectronics. Mater Today, 2006, 9: 46-54 CrossRef Google Scholar

[6] Rutherglen C, Jain D, Burke P. Nanotube electronics for radiofrequency applications. Nat Nanotech, 2009, 4: 811-819 CrossRef ADS Google Scholar

[7] Peng L M, Zhang Z, Wang S. Carbon nanotube electronics: recent advances. Mater Today, 2014, 17: 433-442 CrossRef Google Scholar

[8] Chen Z, Philip Wong H S, Mitra S. Carbon nanotubes for high-performance logic. MRS Bull, 2014, 39: 719-726 CrossRef Google Scholar

[9] International Technology Roadmap for Semiconductors (2013 edition). Google Scholar

[10] Sun J Y C. System scaling for intelligent ubiquitous computing. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2017. 1--7. Google Scholar

[11] Franklin A D. Nanomaterials in transistors: From high-performance to thin-film applications. Science, 2015, 349: aab2750 CrossRef Google Scholar

[12] Zhang H, Xiang L, Yang Y. High-Performance Carbon Nanotube Complementary Electronics and Integrated Sensor Systems on Ultrathin Plastic Foil. ACS Nano, 2018, 12: 2773-2779 CrossRef Google Scholar

[13] Xiang L, Zhang H, Dong G. Low-power carbon nanotube-based integrated circuits that can be transferred to biological surfaces. Nat Electron, 2018, 1: 237-245 CrossRef Google Scholar

[14] Xiang L, Xia F, Zhang H. Wafer?§cale High?Yield Manufacturing of Degradable Electronics for Environmental Monitoring. Adv Funct Mater, 2019, 29: 1905518 CrossRef Google Scholar

[15] Cao Q, Kim H, Pimparkar N. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates. Nature, 2008, 454: 495-500 CrossRef ADS Google Scholar

[16] Sun Y, Wang B W, Hou P X. A carbon nanotube non-volatile memory device using a photoresist gate dielectric. Carbon, 2017, 124: 700-707 CrossRef Google Scholar

[17] Qu T Y, Sun Y, Chen M L. A Flexible Carbon Nanotube Sen?Memory Device. Adv Mater, 2020, 32: 1907288 CrossRef Google Scholar

[18] Yu W J, Chae S H, Lee S Y. Ultra-Transparent, Flexible Single-walled Carbon Nanotube Non-volatile Memory Device with an Oxygen-decorated Graphene Electrode. Adv Mater, 2011, 23: 1889-1893 CrossRef Google Scholar

[19] Le Louarn A, Kapche F, Bethoux J M. Intrinsic current gain cutoff frequency of 30 GHz with carbon nanotube transistors. Appl Phys Lett, 2007, 90: 233108 CrossRef ADS Google Scholar

[20] Bethoux J M, Happy H, Dambrine G. An 8-GHz f/sub t/ carbon nanotube field-effect transistor for gigahertz range applications. IEEE Electron Device Lett, 2006, 27: 681-683 CrossRef ADS Google Scholar

[21] Chen Y Y, Sun Y, Zhu Q B. High-Throughput Fabrication of Flexible and Transparent All-Carbon Nanotube Electronics. Adv Sci, 2018, 5: 1700965 CrossRef Google Scholar

[22] Yamada T, Hayamizu Y, Yamamoto Y. A stretchable carbon nanotube strain sensor for human-motion detection. Nat Nanotech, 2011, 6: 296-301 CrossRef ADS Google Scholar

[23] Ryu S, Lee P, Chou J B. Extremely Elastic Wearable Carbon Nanotube Fiber Strain Sensor for Monitoring of Human Motion. ACS Nano, 2015, 9: 5929-5936 CrossRef Google Scholar

[24] Iijima S. Helical microtubules of graphitic carbon. Nature, 1991, 354: 56-58 CrossRef ADS Google Scholar

[25] Chau R, Datta S, Doczy M. Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications. IEEE Trans Nanotechnol, 2005, 4: 153-158 CrossRef ADS Google Scholar

[26] Zhou X, Park J Y, Huang S. Band Structure, Phonon Scattering, and the Performance Limit of Single-Walled Carbon Nanotube Transistors. Phys Rev Lett, 2005, 95: 146805 CrossRef ADS arXiv Google Scholar

[27] Perebeinos V, Tersoff J, Avouris P. Electron-Phonon Interaction and Transport in Semiconducting Carbon Nanotubes. Phys Rev Lett, 2005, 94: 086802 CrossRef ADS arXiv Google Scholar

[28] Purewal M S, Hong B H, Ravi A. Scaling of Resistance and Electron Mean Free Path of Single-Walled Carbon Nanotubes. Phys Rev Lett, 2007, 98: 186808 CrossRef ADS arXiv Google Scholar

[29] Perebeinos V, Rotkin S V, Petrov A G. The Effects of Substrate Phonon Mode Scattering on Transport in Carbon Nanotubes. Nano Lett, 2009, 9: 312-316 CrossRef ADS arXiv Google Scholar

[30] Park J Y, Rosenblatt S, Yaish Y. Electron-Phonon Scattering in Metallic Single-Walled Carbon Nanotubes. Nano Lett, 2004, 4: 517-520 CrossRef ADS arXiv Google Scholar

[31] Tulevski G S, Franklin A D, Frank D. Toward High-Performance Digital Logic Technology with Carbon Nanotubes. ACS Nano, 2014, 8: 8730-8745 CrossRef Google Scholar

[32] Peng L M, Zhang Z, Wang S. Carbon nanotube electronics: recent advances. Mater Today, 2014, 17: 433-442 CrossRef Google Scholar

[33] Peng L M, Zhang Z, Qiu C. Carbon nanotube digital electronics. Nat Electron, 2019, 2: 499-505 CrossRef Google Scholar

[34] Tans S J, Verschueren A R M, Dekker C. Room-temperature transistor based on a single carbon nanotube. Nature, 1998, 393: 49-52 CrossRef ADS Google Scholar

[35] Martel R, Schmidt T, Shea H R. Single- and multi-wall carbon nanotube field-effect transistors. Appl Phys Lett, 1998, 73: 2447-2449 CrossRef ADS Google Scholar

[36] Zhang Z, Liang X, Wang S. Doping-Free Fabrication of Carbon Nanotube Based Ballistic CMOS Devices and Circuits. Nano Lett, 2007, 7: 3603-3607 CrossRef ADS Google Scholar

[37] Zhang Z, Wang S, Wang Z. Almost Perfectly Symmetric SWCNT-Based CMOS Devices and Scaling. ACS Nano, 2009, 3: 3781-3787 CrossRef Google Scholar

[38] Qiu C, Zhang Z, Xiao M. Scaling carbon nanotube complementary transistors to 5-nm gate lengths. Science, 2017, 355: 271-276 CrossRef ADS Google Scholar

[39] Zhang P, Qiu C, Zhang Z. Performance projections for ballistic carbon nanotube FinFET at circuit level. Nano Res, 2016, 9: 1785-1794 CrossRef Google Scholar

[40] Natarajan S, Agostinelli M, Akbar S, et al. A 14 nm logic technology featuring 2nd-generation finfet, air-gapped interconnects, self-aligned double patterning and a 0.0588 $\mu~$m 2 SRAM cell size. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2014. 1--3. Google Scholar

[41] Franklin A D, Chen Z. Length scaling of carbon nanotube transistors. Nat Nanotech, 2010, 5: 858-862 CrossRef ADS Google Scholar

[42] Qiu C, Liu F, Xu L. Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches. Science, 2018, 361: 387-392 CrossRef ADS Google Scholar

[43] Sabry Aly M M, Gao M, Hills G. Energy-Efficient Abundant-Data Computing: The N3XT 1,000x. Computer, 2015, 48: 24-33 CrossRef Google Scholar

[44] Shulaker M M, Hills G, Park R S. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature, 2017, 547: 74-78 CrossRef ADS Google Scholar

[45] Fleetwood D M. Evolution of Total Ionizing Dose Effects in MOS Devices With Moore's Law Scaling. IEEE Trans Nucl Sci, 2018, 65: 1465-1481 CrossRef ADS Google Scholar

[46] Barnaby H J. Total-Ionizing-Dose Effects in Modern CMOS Technologies. IEEE Trans Nucl Sci, 2006, 53: 3103-3121 CrossRef ADS Google Scholar

[47] Zhu M, Xiao H, Yan G. Radiation-hardened and repairable integrated circuits based on carbon nanotube transistors with ion gel gates. Nat Electron, 2020, 3: 622-629 CrossRef Google Scholar

[48] Flament O, Torres A, Ferlet-Cavrois V. Bias dependence of FD transistor response to total dose irradiation. IEEE Trans Nucl Sci, 2003, 50: 2316-2321 CrossRef ADS Google Scholar

[49] Ding L, Liang S, Pei T. Carbon nanotube based ultra-low voltage integrated circuits: Scaling down to 0.4 V. Appl Phys Lett, 2012, 100: 263116 CrossRef ADS Google Scholar

[50] Nikonov DE, Young IA, Uniform methodology for benchmarking beyond-CMOS logic devices. Proc. IEEE Int. Electron Devices Meeting, 2012, pp. 25.4.1--25.4.4 doi: 10.1109/IEDM.2012.6479102. Google Scholar

[51] Gonzalez R, Horowitz M. Energy dissipation in general purpose microprocessors. IEEE J Solid-State Circuits, 1996, 31: 1277-1284 CrossRef ADS Google Scholar

[52] Hills G, Bardon M G, Doornbos G. Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI. IEEE Trans Nanotechnol, 2018, 17: 1259-1269 CrossRef ADS Google Scholar

[53] Chen B, Zhang P, Ding L. Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits. Nano Lett, 2016, 16: 5120-5128 CrossRef ADS Google Scholar

[54] Yang Y, Ding L, Han J. High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films. ACS Nano, 2017, 11: 4124-4132 CrossRef Google Scholar

[55] Zhong D, Zhang Z, Ding L. Gigahertz integrated circuits based on carbon nanotube films. Nat Electron, 2018, 1: 40-45 CrossRef Google Scholar

[56] Yang S, Ahmed S, Arcot B, et al. A high performance 180 nm generation logic technology. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 1998. 197--200. Google Scholar

[57] Shulaker M M, Hills G, Patil N. Carbon nanotube computer. Nature, 2013, 501: 526-530 CrossRef ADS Google Scholar

[58] Hills G, Lau C, Wright A. Modern microprocessor built from complementary carbon nanotube transistors. Nature, 2019, 572: 595-602 CrossRef ADS Google Scholar

[59] Guo J, Hasan S, Javey A. Assessment of High-Frequency Performance Potential of Carbon Nanotube Transistors. IEEE Trans Nanotechnol, 2005, 4: 715-721 CrossRef ADS Google Scholar

[60] Wang C, Badmaev A, Jooyaie A. Radio Frequency and Linearity Performance of Transistors Using High-Purity Semiconducting Carbon Nanotubes. ACS Nano, 2011, 5: 4169-4176 CrossRef Google Scholar

[61] Zhong D, Shi H, Ding L. Carbon Nanotube Film-Based Radio Frequency Transistors with Maximum Oscillation Frequency above 100 GHz. ACS Appl Mater Interfaces, 2019, 11: 42496-42503 CrossRef Google Scholar

[62] Liu L, Ding L, Zhong D. Carbon Nanotube Complementary Gigahertz Integrated Circuits and Their Applications on Wireless Sensor Interface Systems. ACS Nano, 2019, : acsnano.8b09488 CrossRef Google Scholar

[63] Liang Y, Xiao M, Wu D. Wafer-Scale Uniform Carbon Nanotube Transistors for Ultrasensitive and Label-Free Detection of Disease Biomarkers. ACS Nano, 2020, 14: 8866-8874 CrossRef Google Scholar

[64] Xiao M, Liang S, Han J. Batch Fabrication of Ultrasensitive Carbon Nanotube Hydrogen Sensors with Sub-ppm Detection Limit. ACS Sens, 2018, 3: 749-756 CrossRef Google Scholar

[65] Hu Y, Kang L, Zhao Q. Growth of high-density horizontally aligned SWNT arrays using Trojan catalysts. Nat Commun, 2015, 6: 6099 CrossRef ADS Google Scholar

[66] Si J, Zhong D, Xu H. Scalable Preparation of High-Density Semiconducting Carbon Nanotube Arrays for High-Performance Field-Effect Transistors. ACS Nano, 2018, 12: 627-634 CrossRef Google Scholar

[67] Qiu S, Wu K, Gao B. Solution-Processing of High-Purity Semiconducting Single-Walled Carbon Nanotubes for Electronics Devices. Adv Mater, 2019, 31: 1800750 CrossRef Google Scholar

[68] Brady G J, Way A J, Safron N S. Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs. Sci Adv, 2016, 2: e1601240 CrossRef ADS Google Scholar

[69] Léonard F. Crosstalk between nanotube devices: contact and channel effects. Nanotechnology, 2006, 17: 2381-2385 CrossRef ADS arXiv Google Scholar

[70] Cao Q, Han S, Tulevski G S. Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics. Nat Nanotech, 2013, 8: 180-186 CrossRef ADS Google Scholar

[71] He X, Gao W, Xie L. Wafer-scale monodomain films of spontaneously aligned single-walled carbon nanotubes. Nat Nanotech, 2016, 11: 633-638 CrossRef ADS Google Scholar

[72] Liu L, Han J, Xu L. Aligned, high-density semiconducting carbon nanotube arrays for high-performance electronics. Science, 2020, 368: 850-856 CrossRef ADS Google Scholar

[73] Radosavljevi? M, Heinze S, Tersoff J. Drain voltage scaling in carbon nanotube transistors. Appl Phys Lett, 2003, 83: 2435-2437 CrossRef ADS arXiv Google Scholar

[74] Liu L, Zhao C, Ding L. Drain-engineered carbon-nanotube-film field-effect transistors with high performance and ultra-low current leakage. Nano Res, 2020, 13: 1875-1881 CrossRef Google Scholar

[75] Zhao C, Zhong D, Liu L. Strengthened Complementary Metal-Oxide-Semiconductor Logic for Small-Band-Gap Semiconductor-Based High-Performance and Low-Power Application. ACS Nano, 2020, 14: 15267-15275 CrossRef Google Scholar

[76] Subramanian S, Hosseini M, et al. First monolithic integration of 3D complementary FET (CFET) on 300 mm wafers. In: Proceedings of IEEE Symposium on VLSI Technology, 2020. 20210682. Google Scholar

[77] Shulaker MM, Wu TF, Pal A, et al. Monolithic 3D integration of logic and memory: carbon nanotube FETs, resistive RAM, and silicon FETs. In: Proceedings of IEEE International Electron Devices Meeting, 2014. 14933690. Google Scholar

[78] Liu Y, Zhang J, Peng L M. Three-dimensional integration of plasmonics and nanoelectronics. Nat Electron, 2018, 1: 644-651 CrossRef Google Scholar

[79] Chang SW, Sung PJ, et al. First demonstration of CMOS inverter and 6T-SRAM based on GAA CFETs structure for 3D-IC applications. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), 2019. 19359374. Google Scholar

[80] Zhao Y, Li Q, Xiao X. Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks. ACS Nano, 2016, 10: 2193-2202 CrossRef Google Scholar

[81] Wu T F, Li H, Huang P C. Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration. IEEE J Solid-State Circuits, 2018, 53: 3183-3196 CrossRef ADS Google Scholar

[82] Honda W, Harada S, Ishida S. High-Performance, Mechanically Flexible, and Vertically Integrated 3D Carbon Nanotube and InGaZnO Complementary Circuits with a Temperature Sensor. Adv Mater, 2015, 27: 4674-4680 CrossRef Google Scholar

[83] Brady G J, Way A J, Safron N S. Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs. Sci Adv, 2016, 2: e1601240 CrossRef ADS Google Scholar

[84] Cao Q, Han S J, Tulevski G S. Evaluation of Field-Effect Mobility and Contact Resistance of Transistors That Use Solution-Processed Single-Walled Carbon Nanotubes. ACS Nano, 2012, 6: 6471-6477 CrossRef Google Scholar

[85] Noyce S G, Doherty J L, Cheng Z. Electronic Stability of Carbon Nanotube Transistors Under Long-Term Bias Stress. Nano Lett, 2019, 19: 1460-1466 CrossRef ADS Google Scholar

[86] Liang S, Zhang Z, Pei T. Reliability tests and improvements for Sc-contacted n-type carbon nanotube transistors. Nano Res, 2013, 6: 535-545 CrossRef Google Scholar

  • Figure 1

    (Color online) Transistor scaling trend and innovation opportunities [9] @Copyright 2017 IEEE.

  • Figure 2

    (Color online) (a) Cross-sectional TEM micrographs of P- and N-type FETs, where the channel and gate lengths are respectively 20 and 10 nm @Copyright 2017 AAAS. (b) and (c) Comparisons of gate delay and EDP scaling patterns between CNT- and Si-CMOS FETs. The blue solid line indicates the experiment data fitting for the P-type Si-MOSFETs [39], whereas the green solid line indicates the N-type Si-MOSFETs. Data assessments are all performed at a $V_{\rm~dd}$ of 0.4 V for the CNT CMOS FETs. Besides, the blue and green stars respectively represent the P- and N-type CNTFETs [37]@Copyright 2017 AAAS. protectłinebreak (d) Structural illustration of the CNT FinFET device @Copyright 2016 Springer Nature. (e) Graphs depicting the drastic effects of small persistent $V_{\rm~th}$ changes on the EDP advantages of CNT FinFET versus Si FinFET at varying supply voltages, where $V_{\rm~dd}$ = 0.9 V [38]@Copyright 2016 Springer Nature.

  • Figure 3

    (Color online) (a) Structural illustration of a DS-FET with CNT array channel [41]. (b) Trends of a superexponentially-decaying Dirac source (DS) regarding schematic band structure, DOS, the density of electrons, as well as thermionic emission over a potential barrier in conducting channel. Accordingly, a narrower electron density localization is noted around the Fermi level. Besides, $n(E)$ represents the electron density, and the solid line in $n(E)$ indicates a Boltzmann distribution, where the exponential decay points towards higher energy [41]. (c) Graphs comparing a 400-nm DS-FET (red, 125 CNTs/mm) powered by a 0.5-V low bias with a 14-nm Intel Si MOSFET (black) powered at 0.7 V [39,41]@Copyright 2018 AAAS.

  • Figure 4

    (Color online) (a) Comparison between different circuit architectures [42]. (b) Schematic illustration of a monolithic 3D-integrated chip with nanotube sensors and logic circuits fabricated on top of a silicon chip with high-density interconnects for high bandwidth interlayer communications. In the bottom right part, a cross-sectional TEM micrograph of the four-layer chip is displayed, where each layer is stressed (scale bars = 100 nm). Darker areas of the TEM micrograph represent various oxides like inter-layer or gate dielectrics, whereas brighter areas are wire cross-sections [43] @Copyright 2017 Spring Nature.

  • Figure 5

    (Color online) (a) Schematic of a radiation-immune ion gel-gated CNTFET, whose substrate is polyimide. (b) SEM micrograph of solution-processed CNT film on a polyimide substrate. Inset is an optical image of a finger-structure CNTFET, whose dielectric layer is a printed ion gel. (c) Irradiation schematic of radiation-immune CNTFET with Co-60 $\gamma~$ ray. (d) VTC plots of a CMOS-like inverter ($V_{\rm~dd}$= 1 V) before and after low-dose-rate irradiation. (e) Voltage gain plots of an inverter ($V_{\rm~dd}$= 1 V) against $V_{\rm~in}$ before and after low-dose-rate irradiation. (f) Heating-triggered recovery of VTC performance for the CMOS-like inverter [46]@Copyright 2020 Springer Nature

  • Figure 6

    (Color online) Requirements for transistors in the development of digital integrated circuits.

  • Figure 7

    (Color online) (a) SEM image of deposited CNT network on Si/SiO$_{2}$ substrate. (b) Batch production of CNTFETs on a 4-inch wafer. (c) Transfer characteristics of 120 typical top-gate FET, the voltage bias $V_{\rm~DS}=~- $1 V. (d) Statistic distribution histograms of $V_{\rm~th}$, where the average value is $-0.7$ V and the standard deviation $\sigma~$ = 34 mV from these 120 CNTFETs [52]. protectłinebreak (e) Structural illustration of CMOS FET based on CNT network films. (f) Output patterns of the P-type FET (blue lines) and the N-type FET (red lines) over a $\vert~V_{\rm~GS}\vert~$ range from 0 (bottom) to 2 V (top) with a 0.05-V step size. (g) Micrograph depicting a 4-bit adder [53]. (h) Functionality measurements of eight 4-bit adders at a 2-V $V_{\rm~DD}$ @ Copyright 2016, 2017 American Chemical Society.

  • Figure 8

    (Color online) Circuit schematic (a) and SEM micrograph (b) of a five-stage CNT RO based on stochastically-oriented top gate CNTFET (scale bars = 10 $\mu~$m). In these images, $V_{\rm~dd}$ denotes the supply voltage and GND represents the ground. The loading transistors (red) on the left have 2-folds greater $W_{\rm~ch}$ than the driving transistors (blue) on the left. (c) The output spectrum of a representative five-stage RO with a 115-nm $L_{g}$, where the oscillation frequency is 5.54 GHz [54]@Copyright 2020 Springer Nature.

  • Figure 9

    (Color online) (a) Illustration describing an RV16X-NANO chip, where the die size is 6.912 mm $\times~$ 6.912 mm, with I/O pads arranged in the surroundings. SEM micrographs with rising magnification are displayed below. Wafer-scalable fabrication of RV16X-NANO is achieved fully from the CNFET CMOS in a Si-CMOS- and VLSI-compatible manner. (b) 3D scaled schematic depicting the physical layout of RV16X-NANO, which leverages a novel 3D architecture. The CNFETs in the 3D architecture is arranged in the stack center, where the metal routing is utilized both above and below the device layer [57]@Copyright 2019 Spring Nature.

  • Figure 10

    (Color online) (a) Structural illustration of GSG pads in a CNTRFT. Inset depicts the channel zone architecture, where the air gaps facilitate the parasitic capacitance reduction. (b) Transfer characteristic plot of the CNTRFT. (c) Graphs of pad embedding power gain against gate length, where the lines and dots respectively indicate simulation findings and experimental data. (d) Graphs of pad de-embedding current gain, as well as of (e) intrinsic current gain against the transistor frequency at various gate lengths (90, 50, and 30 nm). The extended lines have a $-$20 dB/dec slope [60]@Copyright 2019 American Chemical Society.

  • Figure 11

    (Color online) (a) Illustration of a CNT IC-based universal interface system of wireless sensors. (b) Circuit schematic of a 5-stage CNT CMOS VCO. (c) Pseudo-colored SEM micrograph of a 5-stage VCO with an extra 1-stage CS amplifier (scale bars = 10 $\mu~$m). The gate is 220 nm in length, and the six N-type FETs (right) all exhibit 2-fold wider channels than the six P-type FETs (left). (d) Graphs describing the oscillation frequency and output power for a representative VCO circuit. The power of the output signal, with a constant value of $-$40 dBm, is nearly independent of $V_{\rm~cont}$, while regarding the $V_{\rm~cont}$-dependent frequency, the relevant average sensitivity value is 0.68 GHz/V [61]@Copyright 2019 American Chemical Society.

  • Figure 12

    (Color online) (a) The top left part shows a picture of CNT floating-gate (FG) FET produced on a 10-cm wafer for biosensor applications. The top right part represents the sensing principle of an FG-FET biosensor. The bottom gives an overall biosensor schematic. (b) DNA detection calibration graph at a $V_{\rm~ds}$ of $-0.1$ V and a $V_{\rm~gs}$ of $-0.7$ V. Black dashed line refers to the blank control immersed in 0.1 $\times~$ PBS. A 60-aM theoretical LOD is yielded by extending the linear fit plots. Inset describes the correlation between the concentration and the response for five different biosensors. The mean responses of the five devices are linearly fitted against the DNA concentration logarithmic. (c) Calibration graphs of CNT FG-FET biosensors modified with aptamer, which can achieve MV detection at concentrations varying from 6 to 6 $\times~$ 10$^{6}$ particles/$\mu~$L under $V_{\rm~ds}$ and $V_{\rm~gs}$ of $-$0.1 and $-$0.7 V, respectively. The black dashed line indicates the noise intensity ($~\sim $3.7) during a test of the blank control in 1 $\times~$ PBS [62]@Copyright 2020 American Chemical Society.

  • Figure 13

    (Color online) (a)–(c) Process schematics for a wafer-scale A-CNT fabrication. (d) Optimal image of the deposition setup for depositing CNTs on a 4-inch silicon wafer. (e) to (g) SEM micrographs of an as-deposited A-CNT, which are acquired at various magnifications by adopting a 40-mg/ml optimal concentration of CNT solution. (h) Graph of semiconducting purity against array density. The blue hollow box represents the utility zone. Our results are within the pink zone, where a typical result is denoted as a red hollow star. (i) Output patterns for the CNTFET. (j) Power spectrum of an RO having an 80.6-GHz highest-stage switching frequency [71]@Copyright 2020 AAAS.

  • Figure 14

    (Color online) (a) Structural illustration of an FBG-FET. (b) Schematic band structures of normal (red curves) and FBG (blue curves) CNTFETs at small (upper) and large biases (lower). (c) Transfer patterns of a self-aligned (SA) gate versus an FBG CNTFET under a high bias $V_{\rm~ds}$ of $-2$ V. (d) Circuit schematic of a SCMOS logic gate. (e) Voltage transfer curves of an inverter based on CNT SCMOS at various supply voltages [73]@Copyright 2019 Springer Nature, and [74]@Copyright 2020 American Chemical Society.

  • Figure 15

    (Color online) Schematic diagram of three-dimensional integration of sensing, storage, and computing based on carbon nanotube-based technology.

  • Table 1  

    Table 1Comparison of various FETs based on individual CNTs

    Ref.PolarityContact typeGate structure$I_{\rm~on}$SS (mV/dec)$d$ (CNT) (nm)$L_{g}$$\mu$ (cm$^{2}$/V$\cdot$s)
    [33]P Schottky contact Bottom gate $\sim~$nA 1.4 400 nm
    [34]P Schottky contact Bottom gate $\sim~$nA 1.6 1 $\mu$m 20
    [35]N Ohmic contact Top gate 20 $\mu~$A 250 2 300 nm
    ($V_{\rm~gs}=-2$ V)
    [36] P, N Ohmic contact Top gate 11.5/11 $\mu$A (P/N) 90/100 (P/N) 2 3 $\mu~$m 3300/3000
    ($V_{\rm~gs}=-2$ V)
    [37] P, NOhmic contact Top gate 15 $\mu~$A60/70 (P/N) 1.3 10 nm
    ($V_{\rm~gs}=-0.4$ V)
    [40] P Ohmic contact Local bottom gate 10 $\mu~$A 85 1–1.2 20 nm
    ($V_{\rm~gs}=-0.5$ V)
qqqq

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