SCIENCE CHINA Information Sciences, Volume 64 , Issue 10 : 201402(2021) https://doi.org/10.1007/s11432-021-3271-8

Carbon nanotube-based CMOS transistors and integrated circuits

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  • ReceivedMar 31, 2021
  • AcceptedMay 24, 2021
  • PublishedAug 20, 2021



This work was supported by National Key Research Development Program (Grant No. 2016YFA0201901) and Beijing Municipal Science and Technology Commission (Grant No. Z181100004418011).


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  • Figure 1

    (Color online) Transistor scaling trend and innovation opportunities [9] @Copyright 2017 IEEE.

  • Figure 2

    (Color online) (a) Cross-sectional TEM micrographs of P- and N-type FETs, where the channel and gate lengths are respectively 20 and 10 nm @Copyright 2017 AAAS. (b) and (c) Comparisons of gate delay and EDP scaling patterns between CNT- and Si-CMOS FETs. The blue solid line indicates the experiment data fitting for the P-type Si-MOSFETs [39], whereas the green solid line indicates the N-type Si-MOSFETs. Data assessments are all performed at a $V_{\rm~dd}$ of 0.4 V for the CNT CMOS FETs. Besides, the blue and green stars respectively represent the P- and N-type CNTFETs [37]@Copyright 2017 AAAS. protectłinebreak (d) Structural illustration of the CNT FinFET device @Copyright 2016 Springer Nature. (e) Graphs depicting the drastic effects of small persistent $V_{\rm~th}$ changes on the EDP advantages of CNT FinFET versus Si FinFET at varying supply voltages, where $V_{\rm~dd}$ = 0.9 V [38]@Copyright 2016 Springer Nature.

  • Figure 3

    (Color online) (a) Structural illustration of a DS-FET with CNT array channel [41]. (b) Trends of a superexponentially-decaying Dirac source (DS) regarding schematic band structure, DOS, the density of electrons, as well as thermionic emission over a potential barrier in conducting channel. Accordingly, a narrower electron density localization is noted around the Fermi level. Besides, $n(E)$ represents the electron density, and the solid line in $n(E)$ indicates a Boltzmann distribution, where the exponential decay points towards higher energy [41]. (c) Graphs comparing a 400-nm DS-FET (red, 125 CNTs/mm) powered by a 0.5-V low bias with a 14-nm Intel Si MOSFET (black) powered at 0.7 V [39,41]@Copyright 2018 AAAS.

  • Figure 4

    (Color online) (a) Comparison between different circuit architectures [42]. (b) Schematic illustration of a monolithic 3D-integrated chip with nanotube sensors and logic circuits fabricated on top of a silicon chip with high-density interconnects for high bandwidth interlayer communications. In the bottom right part, a cross-sectional TEM micrograph of the four-layer chip is displayed, where each layer is stressed (scale bars = 100 nm). Darker areas of the TEM micrograph represent various oxides like inter-layer or gate dielectrics, whereas brighter areas are wire cross-sections [43] @Copyright 2017 Spring Nature.

  • Figure 5

    (Color online) (a) Schematic of a radiation-immune ion gel-gated CNTFET, whose substrate is polyimide. (b) SEM micrograph of solution-processed CNT film on a polyimide substrate. Inset is an optical image of a finger-structure CNTFET, whose dielectric layer is a printed ion gel. (c) Irradiation schematic of radiation-immune CNTFET with Co-60 $\gamma~$ ray. (d) VTC plots of a CMOS-like inverter ($V_{\rm~dd}$= 1 V) before and after low-dose-rate irradiation. (e) Voltage gain plots of an inverter ($V_{\rm~dd}$= 1 V) against $V_{\rm~in}$ before and after low-dose-rate irradiation. (f) Heating-triggered recovery of VTC performance for the CMOS-like inverter [46]@Copyright 2020 Springer Nature

  • Figure 6

    (Color online) Requirements for transistors in the development of digital integrated circuits.

  • Figure 7

    (Color online) (a) SEM image of deposited CNT network on Si/SiO$_{2}$ substrate. (b) Batch production of CNTFETs on a 4-inch wafer. (c) Transfer characteristics of 120 typical top-gate FET, the voltage bias $V_{\rm~DS}=~- $1 V. (d) Statistic distribution histograms of $V_{\rm~th}$, where the average value is $-0.7$ V and the standard deviation $\sigma~$ = 34 mV from these 120 CNTFETs [52]. protectłinebreak (e) Structural illustration of CMOS FET based on CNT network films. (f) Output patterns of the P-type FET (blue lines) and the N-type FET (red lines) over a $\vert~V_{\rm~GS}\vert~$ range from 0 (bottom) to 2 V (top) with a 0.05-V step size. (g) Micrograph depicting a 4-bit adder [53]. (h) Functionality measurements of eight 4-bit adders at a 2-V $V_{\rm~DD}$ @ Copyright 2016, 2017 American Chemical Society.

  • Figure 8

    (Color online) Circuit schematic (a) and SEM micrograph (b) of a five-stage CNT RO based on stochastically-oriented top gate CNTFET (scale bars = 10 $\mu~$m). In these images, $V_{\rm~dd}$ denotes the supply voltage and GND represents the ground. The loading transistors (red) on the left have 2-folds greater $W_{\rm~ch}$ than the driving transistors (blue) on the left. (c) The output spectrum of a representative five-stage RO with a 115-nm $L_{g}$, where the oscillation frequency is 5.54 GHz [54]@Copyright 2020 Springer Nature.

  • Figure 9

    (Color online) (a) Illustration describing an RV16X-NANO chip, where the die size is 6.912 mm $\times~$ 6.912 mm, with I/O pads arranged in the surroundings. SEM micrographs with rising magnification are displayed below. Wafer-scalable fabrication of RV16X-NANO is achieved fully from the CNFET CMOS in a Si-CMOS- and VLSI-compatible manner. (b) 3D scaled schematic depicting the physical layout of RV16X-NANO, which leverages a novel 3D architecture. The CNFETs in the 3D architecture is arranged in the stack center, where the metal routing is utilized both above and below the device layer [57]@Copyright 2019 Spring Nature.

  • Figure 10

    (Color online) (a) Structural illustration of GSG pads in a CNTRFT. Inset depicts the channel zone architecture, where the air gaps facilitate the parasitic capacitance reduction. (b) Transfer characteristic plot of the CNTRFT. (c) Graphs of pad embedding power gain against gate length, where the lines and dots respectively indicate simulation findings and experimental data. (d) Graphs of pad de-embedding current gain, as well as of (e) intrinsic current gain against the transistor frequency at various gate lengths (90, 50, and 30 nm). The extended lines have a $-$20 dB/dec slope [60]@Copyright 2019 American Chemical Society.

  • Figure 11

    (Color online) (a) Illustration of a CNT IC-based universal interface system of wireless sensors. (b) Circuit schematic of a 5-stage CNT CMOS VCO. (c) Pseudo-colored SEM micrograph of a 5-stage VCO with an extra 1-stage CS amplifier (scale bars = 10 $\mu~$m). The gate is 220 nm in length, and the six N-type FETs (right) all exhibit 2-fold wider channels than the six P-type FETs (left). (d) Graphs describing the oscillation frequency and output power for a representative VCO circuit. The power of the output signal, with a constant value of $-$40 dBm, is nearly independent of $V_{\rm~cont}$, while regarding the $V_{\rm~cont}$-dependent frequency, the relevant average sensitivity value is 0.68 GHz/V [61]@Copyright 2019 American Chemical Society.

  • Figure 12

    (Color online) (a) The top left part shows a picture of CNT floating-gate (FG) FET produced on a 10-cm wafer for biosensor applications. The top right part represents the sensing principle of an FG-FET biosensor. The bottom gives an overall biosensor schematic. (b) DNA detection calibration graph at a $V_{\rm~ds}$ of $-0.1$ V and a $V_{\rm~gs}$ of $-0.7$ V. Black dashed line refers to the blank control immersed in 0.1 $\times~$ PBS. A 60-aM theoretical LOD is yielded by extending the linear fit plots. Inset describes the correlation between the concentration and the response for five different biosensors. The mean responses of the five devices are linearly fitted against the DNA concentration logarithmic. (c) Calibration graphs of CNT FG-FET biosensors modified with aptamer, which can achieve MV detection at concentrations varying from 6 to 6 $\times~$ 10$^{6}$ particles/$\mu~$L under $V_{\rm~ds}$ and $V_{\rm~gs}$ of $-$0.1 and $-$0.7 V, respectively. The black dashed line indicates the noise intensity ($~\sim $3.7) during a test of the blank control in 1 $\times~$ PBS [62]@Copyright 2020 American Chemical Society.

  • Figure 13

    (Color online) (a)–(c) Process schematics for a wafer-scale A-CNT fabrication. (d) Optimal image of the deposition setup for depositing CNTs on a 4-inch silicon wafer. (e) to (g) SEM micrographs of an as-deposited A-CNT, which are acquired at various magnifications by adopting a 40-mg/ml optimal concentration of CNT solution. (h) Graph of semiconducting purity against array density. The blue hollow box represents the utility zone. Our results are within the pink zone, where a typical result is denoted as a red hollow star. (i) Output patterns for the CNTFET. (j) Power spectrum of an RO having an 80.6-GHz highest-stage switching frequency [71]@Copyright 2020 AAAS.

  • Figure 14

    (Color online) (a) Structural illustration of an FBG-FET. (b) Schematic band structures of normal (red curves) and FBG (blue curves) CNTFETs at small (upper) and large biases (lower). (c) Transfer patterns of a self-aligned (SA) gate versus an FBG CNTFET under a high bias $V_{\rm~ds}$ of $-2$ V. (d) Circuit schematic of a SCMOS logic gate. (e) Voltage transfer curves of an inverter based on CNT SCMOS at various supply voltages [73]@Copyright 2019 Springer Nature, and [74]@Copyright 2020 American Chemical Society.

  • Figure 15

    (Color online) Schematic diagram of three-dimensional integration of sensing, storage, and computing based on carbon nanotube-based technology.

  • Table 1  

    Table 1Comparison of various FETs based on individual CNTs

    Ref.PolarityContact typeGate structure$I_{\rm~on}$SS (mV/dec)$d$ (CNT) (nm)$L_{g}$$\mu$ (cm$^{2}$/V$\cdot$s)
    [33]P Schottky contact Bottom gate $\sim~$nA 1.4 400 nm
    [34]P Schottky contact Bottom gate $\sim~$nA 1.6 1 $\mu$m 20
    [35]N Ohmic contact Top gate 20 $\mu~$A 250 2 300 nm
    ($V_{\rm~gs}=-2$ V)
    [36] P, N Ohmic contact Top gate 11.5/11 $\mu$A (P/N) 90/100 (P/N) 2 3 $\mu~$m 3300/3000
    ($V_{\rm~gs}=-2$ V)
    [37] P, NOhmic contact Top gate 15 $\mu~$A60/70 (P/N) 1.3 10 nm
    ($V_{\rm~gs}=-0.4$ V)
    [40] P Ohmic contact Local bottom gate 10 $\mu~$A 85 1–1.2 20 nm
    ($V_{\rm~gs}=-0.5$ V)

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