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SCIENCE CHINA Information Sciences, Volume 64 , Issue 6 : 160402(2021) https://doi.org/10.1007/s11432-021-3220-0

A survey of in-spin transfer torque MRAM computing

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  • ReceivedJan 15, 2021
  • AcceptedMar 17, 2021
  • PublishedMay 10, 2021

Abstract


Acknowledgment

This work was supported by National Natural Science Foundation of China (Grant No. 61904028).


References

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  • Figure 1

    (Color online) (a) According to the device characteristics, different bit-cell types and structures can be implemented for desired performance in specific scenarios. (b) Commonly, circuit-level reconfiguration is realized using carefully designed peripheral circuits, including reading/writing drivers, sense amplifiers, and controllers. Basic functions are targeted, including storage and the computing unit. (c) Architecture-level reconfiguration is mainly focused on application ($X$ or $Y$) and follows instructions from the core processing unit to execute assigned tasks.

  • Figure 2

    (Color online) Modified von-Neumann structure with in-memory computing. (a) PEs with memory hierarchies; (b) PEs with 3D stacked DRAM; (c) in-memory analog computing with SRAM and NVM; (d) three IMC modes.

  • Figure 3

    (Color online) MRAM bit-cell, main array, and peripheral blocks. (a) Bit-cell access bias; (b) latch-type voltage-mode sensing scheme and simulated transient waveform; (c) main STT-MRAM building blocks (1T-1M bit-cell).

  • Figure 4

    (Color online) Literature study of silicon-verified MRAM bit-cell structure. (a) The size of the bit-cells and their compatible CMOS process in MRAM, SRAM, and RRAM. (b) 1T-1M. The 2T-2M cell circuit is demonstrated as a suitable candidate for low-capacity and high-performance designs.

  • Figure 5

    (Color online) (a) A common structure of analog computation based IMC. WL driver, reference tree, and modified sensing amplifier are included. (b) Writing-only IMC circuit, basic Boolean logic functions can be realized.

  • Figure 6

    (Color online) Structure of a time-domain computing-in-memory macro. The architecture of the CNN accelerator with 4 CIM macros. Each CIM macro contains an MRAM array. A row-wise digital-time-converter is used to convert an activation into a time pulse signal. Both ADC and DAC are implemented at each column to provide MAC read-out and analog write-in. Similar to prior schemes, global SRAMs are used to store weight and input/output activation data before being fetched into CIM macro. A date manager is used to manage data sequencing and pre-/post-processing.

  • Figure 7

    (Color online) Sparse realization in unreliable MRAM for CNN [101]. (a) Patch bank structure of MRAM; (b) the flowchart of sparse realization in unreliable MRAM; (c) the visualization of a retrained model on CIFAR-10. The increased sparsity of in-MRAM can lead to the generation of incorrect labels during classification.

  • Table 1  

    Table 1Summary of main acronyms

    Acronym Definition Acronym Definition
    STT Spin transfer torque NVM Non-volatile memories
    MRAM Magnetoresistive random access memory RRAM Resistive random access memory
    IMC In-memory computing PCM Phase change memory
    NMC Near-memory computing LIM Logic-in-memory
    MTJ Magnetic tunnel junction SRAM/DRAM Static/dynamic random access memory
    SOT Spin orbit torque MAC Multiply-and-accumulate
    VCMA Voltage controlled magnetic anisotropy CD Critical dimension
    VG-SHE Voltage-gated spin hall effect ECC Error correction coding
    TST Toggle spin torques PPA Power-performance-area
    TMR Tunnel magnetoresistance ratio SA Sense amplifier
    PMA Perpendicular magnetic anisotropy VSA/CSA Voltage-type/current-type SA
    PEs Processing elements ADC Analog-to-digital converter
    PTL Pass-transistor-logic FA Full adder
    WL/BL/SL Word-line/bit-line/source-line FDSOI Fully depleted silicon-on-insulator
    FinFET Fin field-effect transistor PUF Physical unclonable function
    PVT Process-voltage-temperature TRNG True random number generator
    FeFET Ferroelectric field effect transistors DNN/CNN/BNN Deep/convolutional/binary neural network
    SoC System-on-chip MeRAM Magnetoelectric random access memory
  • Table 2  

    Table 2Survey of recent emerging memory based MAC operation

    CMOS Memory Bit-cellArray Tape-outMACSpeed-up Energy Application
    DAC'16 [49] N/A RRAM 1T1R 512$\times$512 No DA-AD 1000$\times$ N/A Inference
    ISCA'16 [50] 32-nmRRAM 1T1R 128$\times$128 No DA-AD 14.8$\times$ 380 GOPS/W Inference
    Nature'18 [51] 90-nmPCM 3T1C 512$\times$512 No DA-AD N/A 119.7 TOPS/W Inference+training
    Nat.Elec.'18 [52]N/A RRAM 1T1R 128$\times$64 Yes DA-AD N/A 17$\times$ Inference
    ISSCC'18 [53] 55-nmRRAM 1T1R 512$\times$256 Yes AD 2$\times$ N/A Inference
    ISSCC'19 [54] 55-nmRRAM 1T1R 256$\times$512 Yes AD 1.3$\times$ 53.17 TOPS/W Inference
    VLSI'18 [55] 180/40-nmRRAM 1T1R 2 Mb/4 Mb Yes AD N/A 66.5 TOPS/WInference
    NIPS'18 [56] 22-nmSTT-MRAM 1T1M 40 Mb Yes SRAM N/A 9.9 TOPS/W Inference
    IEDM'18 [57] 130-nmRRAM 2T2R N/A Yes SA+logicN/A 25 nJ/img/Minst Inference
    DAC'18 [58] 45-nmSOT-MRAM 2T1M N/A No IMC 4.3$\times$ 0.74 $\mu$J/img/Minst Inference
    TVLSI'19 [59] 28-nmSOT-MRAM 2T1M 128$\times$256No IMC 12.3$\times$ 96.6 image/s/W Inference
    ISCAS'19 [60] 22-nmSTT-MRAM 1T1M 64$\times$576 No AD 70$\times$ 4.5$\times$ Inference
    ISSCC'20 [61] 130-nm RRAM 1T1R 158.8 Kbit Yes DA-AD N/A 78.4 TOPS/W Inference
  • Table 3  

    Table 3Survey of In-MRAM computing

    CMOS Memory Bit-cell OperationIMC with SA type Energy efficiency Throughout
    JSSC'15 [26] 90-nm STT 4T2M Read Pass-transistor CSA 48.3% improved 5$\times$5 PE
    TED'19 [68] 40-nm STT 1T1M Write Bit-cell CSA 237.3 fJ/bit N/A
    MEJ'18 [69]45-nm STT 1T1M Read Dual references CSA 10 fJ/bit-wise bit-wise
    TVLSI'18 [70] N/A eNVM 1T1R Read References VSA 38% improved bit-wise
    VLSI'18 [71] 45-nm STT 1T1M Read References CSA N/A bit-wise/DNN
    DAC'18 [58] 45-nm SOT 2T1M Read References VSA 94 $\times$ N/A
    Intermag'18 [72]40-nm STT 1T2MReadMTJ+referencesCSA N/A N/A
    TED'17 [73] N/A VCMA1M Write+readMTJ Crossbar 12 fJ/bit N/A
    DAC'19 [74] 45-nm SOT 2T1M Read References VSA N/A 412.28 K/W
    TVLSI'19 [75] 28-nm STT 2T1M Write/read Threshold+references CSA 68.5% saving vs. FPGA 235.1 image/s
    TVLSI'19 [59] 28-nm SOT 2T1M Write+readBit-cell CSA 1.41 W (CIFAR-10) 96.6-image/s/W
    Tnano'19 [76] 40-nm VG-SHE 1T1M Write Bit-cell Crossbar 63.8 fJ/bit/FA bit-wise
    VLSI'20 [34] 22-nm SOT 2T1M Read Analog IMC N/A N/A N/A
    ISSCC'20 [31] 22-nm STT 1T1M Read Near-memory CSA 0.23 pJ/bit read 42.67 GB/s read
  • Table 4  

    Table 4Writing/reading failure mechanisms and key causes

    Affect Mechanisms Major factors
    4*Read Decision fault Process variations, limited TMR, low supply voltage
    Read disturb Read and write share the same path, growing with technology scaling
    Incorrect read fault Opposite temperature dependence resistance, parasitic effects, tiny SA sensing margin
    Retention failures Intrinsic thermal instability, thermal noise
    4*Write Transition faults Stochastic nature of write operation, thermal fluctuations
    Coupling faults Neighboring cells switching
    Write polarization asymmetryHigher $P$-AP switching current, varied writing time
  • Table 5  

    Table 5Survey of MRAM based neural network

    CMOS Tape-out Memory CapacityCIM Speed up Energy saving Area Application
    NIPS'18 [56] 22-nm $\checkmark$ STT 40 Mb $\checkmark$ N/A 9.9 TOPS/W N/ANLP
    IEDM'18 [90] 45/28-nm$\checkmark$ STT 32 Kb $\checkmark$ N/A 82% N/AComputer vision
    DAC'18 [58] 45-nm $\times$ SOT N/A $\times$ 4.3$\times$ 67% N/AComputer vision
    TVLSI'19 [59] 28-nm $\times$ SOT 2048$\times$256 $\checkmark$ 12.3$\times$ 60.8% N/A Computer vision
    TVLSI'19 [75]28-nm $\times$ SOT N/A $\checkmark$ 4.7$\times$ 29% N/A Computer vision
    JETCAS'19 [29] 22-nm $\times$ STT 8 Mb $\times$ 4.85$\times$ 83.5% N/A Computer vision
    DAC'19 [91] N/A $\times$ STT N/A $\times$ N/A 79.4% 57%Computer vision
    DATE'19 [92] 28-nm $\times$ SOT 1024$\times$512$\checkmark$ 2.12$\times$ 14% N/A Computer vision
    ASP-DAC'20 [93]45-nm$\times$ SOT 256$\times$512 $\checkmark$ N/A 63% 7.9%Computer vision
    VLSI'20 [34]22-nm $\checkmark$ SOT $\times$ $\checkmark$ N/A N/A N/A DNN
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