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SCIENCE CHINA Information Sciences, Volume 64 , Issue 11 : 219401(2021) https://doi.org/10.1007/s11432-020-3123-2

Design of a high-performance 12T SRAM cell for single event upset tolerance

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  • ReceivedJul 3, 2020
  • AcceptedNov 16, 2020
  • PublishedSep 3, 2021

Abstract

There is no abstract available for this article.


Acknowledgment

This work was supported by the Innovation Foundation of Harbin Institute of Technology (Grant Nos. HIT.NSRIF.2019007, 20190028).


References

[1] C. Qi, L. Xiao, T. Wang, et al. A Highly Reliable Memory Cell Design Combined with Layout-Level Approach to Tolerant Single-Event Upsets. IEEE Trans. Device Mater. Rel., 2016, 16:388-395. Google Scholar

[2] Chen J, Chen S, Liang B. Simulation Study of the Layout Technique for P-hit Single-Event Transient Mitigation via the Source Isolation. IEEE Trans Device Mater Relib, 2012, 12: 501-509 CrossRef Google Scholar

[3] Naga Raghuram C, Gupta B, Kaushal G. Double Node Upset Tolerant RHBD15T SRAM Cell Design for Space Applications. IEEE Trans Device Mater Relib, 2020, 20: 181-190 CrossRef Google Scholar

  • Figure 1

    (Color online) (a) Schematic diagram of the proposed HP12T SRAM cell; (b) normal operation diagram of HP12T SRAM cell; (c) the layout of HP12T SRAM cell; (d) ion striking on node Q; (e) ion striking on node S0; (f) ion striking on node S1;protectłinebreak (g) comparisons of different SRAMs' performance (please refer to [1]for understanding the structure of each SRAM cell listed here).

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