SCIENCE CHINA Information Sciences, Volume 63 , Issue 10 : 202401(2020) https://doi.org/10.1007/s11432-020-2866-0

Efficient 16 Boolean logic and arithmetic based on bipolar oxide memristors

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  • ReceivedMar 15, 2020
  • AcceptedApr 8, 2020
  • PublishedAug 26, 2020



This work was supported by National Key RD Program of China (Grant No. 2017YFA0207600), National Natural Science Foundation of China (Grant Nos. 61925401, 61674006, 61927901, 61421005), and the 111 Project (Grant No. B18001). Yuchao YANG acknowledges the support from Beijing Academy of Artificial Intelligence (BAAI) and the Tencent Foundation through the Xplorer Prize.


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  • Figure 1

    (Color online) (a) Schematic of the Pt/Ta/Ta$_{2}$O$_{5}$/Pt/Ti device structure. (b) TEM image of the Pt/Ta/Ta$_{2}$O$_{5}$/Pt/Ti structure. Scale bar: 20 nm. (c) Typical resistive switching characteristics of the Pt/Ta/Ta$_{2}$O$_{5}$/Pt/Ti devices. (d) Current response under voltage pulse. Constant read voltage of 0.1 V was applied to the TE terminal.

  • Figure 2

    (Color online) (a) Schematic diagram of implementing three logical operations. (b) Experimental demonstration of AND, OR, and XOR in pulse measurements. The initial read operation (green background) is to know the initial resistance state and verify the correctness of the logic operation. In practical applications, only XOR logic needs to read the initial resistance state to determine the voltage input port. Constant read voltage of 0.1 V was applied to the TE terminal during the entire logic operations. $V_{\rm~set}$ added to the TE is 2.3 V, 100 ns and $V_{\rm~reset}$ added to the BE is 2.5 V, 100 ns.

  • Figure 3

    (Color online) (a) Operating sequence of the 1-bit binary full adder; (b) calculation process diagram for the typical input combination (1+1+1); (c) resistance evolution of three devices for input combination (1+1+1); (d) experimental results for all 8 possible input combinations.

  • Figure 4

    (Color online) (a) Operating sequence of the 2-bit multiplier; (b) calculation process diagram for the typical input combination (11$\times$10); (c) resistance evolution of five devices for input combination (11$\times$10); (d) experimental results for all 16 possible input combinations.

  • Table 1  

    Table 1Complete 16 Boolean logic implementations

    5* XOR$p$$q$$Z$TEBE$Z_{m}$TEBE$Z'$
    4* XNOR00$p$1$q$1
    4* NAND00$p$$q$10101
    4* NOR00$p$$q$00101
    4* NOT $p$00$p$101
    4* NOT $q$00$p$1$q$1
  • Table 2  

    Table 2Comparison of XOR logic operation and 1-bit full adder schemes

    2*ReferenceXOR1-bit full adder
    Device numberStepDevice numberStep
    This study1236