SCIENCE CHINA Information Sciences, Volume 63 , Issue 10 : 201401(2020) https://doi.org/10.1007/s11432-020-2806-8

Graphene-based vertical thin film transistors

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  • ReceivedJan 4, 2020
  • AcceptedFeb 16, 2020
  • PublishedJul 16, 2020



The work of Yuan LIU was supported by National Natural Science Foundation of China (Grant Nos. 51802090, 61874041, 51991341) and Hunan Science Fund for Excellent Young Scholars (Grant No. 812019037).


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  • Figure 1

    (Color online) Three-dimensional perspective schematics of the perforated electrode based VFET (a) and nanowire based VFET (b), where the gate field could penetrate through the “holes" of the electrode, and hence modulate the conductivity of the channel material. Within this structure, the channel length is simply defined by the distance between source-drain electrodes. Schematic illustrations of the cross-sectional view of graphene-based top-gated VFET (c) and back-gated VFET (d). (e) A schematic of the conventional planar transistor, where the channel length is defined by the lithography resolution.

  • Figure 2

    (Color online) (a) The unique negative resistance characteristic of the graphene-BN-graphene tunneling vertical transistor [86]@Copyright 2013 Springer Nature. Band-diagram of the vertical thermionic transistor at OFF state (b) and ON state (c). A negative gate voltage increases the Schottky barrier height, resulting in the OFF state. On the other hand, when applying positive gate voltage to the transistor, the Schottky barrier is decreased and the device is at ON state. protectłinebreak (d) The output characteristic of a typical thermionic vertical transistors.

  • Figure 3

    (Color online) (a) Resistor network model of VFETs [26]@Copyright 2019 American Chemical Society. (b) A schematic of the cross-sectional view of the organic VFET device based on graphene-P3HT heterostructure [34]@Copyright 2015 American Chemical Society. Transfer characteristics of self-aligned graphene-InAs-metal VFET in negative bias region (c) and positive bias region (d) [26]@Copyright 2019 American Chemical Society. (e) The relationship between current density and the series graphene lengths in both experiment and calculated results [26]@Copyright 2019 American Chemical Society.

  • Figure 4

    (Color online) (a) A schematic of conventional planar structure with the brittle material as the channel, where the channel crack could result in overall device failure [87]@Copyright 2014 American Chemical Society. (b) A schematic of the VFET with the brittle material as the channel, and the vertical current transport is largely unaffected by the in-plane crack in the brittle films [87]@Copyright 2014 American Chemical Society. (c) Image of IGZO-graphene VFETs integrated on a PET flexible substrate [87]@Copyright 2014 American Chemical Society. (d) Normalized conductance of planar IGZO FET (red) and IGZO-graphene VFETs (black) under various bending radius [87]@Copyright 2014 American Chemical Society. (e) Normalized conductance of the planar IGZO structure (red) and vertical IGZO-graphene structure (black) at various bending cycles, showing better robustness of the VFET architecture [87]@Copyright 2014 American Chemical Society.

  • Figure 5

    (Color online) (a) Photograph of vertical transistors integrated on a 6-inch transparent glass wafer with 2000 devices (left) [42]@Copyright 2013 American Chemical Society. Photograph of vertical transistors integrated on a 2-inch wafer with an array of 1620 devices (right) [87]@Copyright 2014 American Chemical Society. (b) Schematic illustration of current path between vertically integrated transistors in the conventional stacking approach [75]@Copyright 2019 American Chemical Society. (c) Schematic illustration of current path between vertically integrated transistors in the remote gating approach [75]@Copyright 2019 American Chemical Society. (d) Schematic of the cross section of a remote gating vertical-Schottky barrier transistor with gate electrodes positioned at different locations [75]@Copyright 2019 American Chemical Society.