This work was partly supported by National Natural Science Foundation of China (Grant Nos. 61421005, 61851401, 61822401, 61604006) and the 111 Project (Grant No. B18001).
[1] Ionescu A M, Riel H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature, 2011, 479: 329-337 CrossRef PubMed ADS Google Scholar
[2] Sarkar D, Xie X J, Liu W. A subthermionic tunnel field-effect transistor with an atomically thin channel. Nature, 2015, 526: 91-95 CrossRef PubMed ADS Google Scholar
[3] Zhao Y, Wu C L, Huang Q Q. A Novel Tunnel FET Design Through Adaptive Bandgap Engineering With Constant Sub-Threshold Slope Over 5 Decades of Current and High $\text{I}_{\mathrm~{ON}}/\text{I}_{\mathrm~{OFF}}$ Ratio. IEEE Electron Device Lett, 2017, 38: 540-543 CrossRef ADS Google Scholar
[4] Dey A W, Borg B M, Ganjipour B. High-Current GaSb/InAs(Sb) Nanowire Tunnel Field-Effect Transistors. IEEE Electron Device Lett, 2013, 34: 211-213 CrossRef ADS Google Scholar
[5] Liu Y, Weiss N O, Duan X D. Van der Waals heterostructures and devices. Nat Rev Mater, 2016, 1: 16042 CrossRef ADS Google Scholar
[6] Roy T, Tosun M, Cao X. Dual-gated MoS2/WSe2 van der Waals tunnel diodes and transistors.. ACS Nano, 2015, 9: 2071-2079 CrossRef PubMed Google Scholar
[7] Roy T, Tosun M, Hettick M. 2D-2D tunneling field-effect transistors using WSe$_{2}$/SnSe$_{2}$ heterostructures. Appl Phys Lett, 2016, 108: 083111 CrossRef ADS Google Scholar
[8] Xu J, Jia J Y, Lai S. Tunneling field effect transistor integrated with black phosphorus-MoS$_{2}$ junction and ion gel dielectric. Appl Phys Lett, 2017, 110: 033103 CrossRef ADS Google Scholar
[9] Yan X, Liu C S, Li C, et al. Tunable SnSe$_2$/WSe$_2$ heterostructure tunneling field effect transistor. Small, 2017, 1701478. Google Scholar
[10] Li X F, Gao T T, Wu Y Q. Development of two-dimensional materials for electronic applications. Sci China Inf Sci, 2016, 59: 061405 CrossRef Google Scholar
[11] Xie Q, Chen C, Liu M J. Short-channel effects on the static noise margin of 6T SRAM composed of 2D semiconductor MOSFETs. Sci China Inf Sci, 2019, 62: 062404 CrossRef Google Scholar
[12] Krishnamoorthy S, Lee Ii E W, Lee C H. High current density 2D/3D MoS$_{2}$/GaN Esaki tunnel diodes. Appl Phys Lett, 2016, 109: 183505 CrossRef ADS arXiv Google Scholar
[13] Zhang B X, An X, Liu P Q. Improvement of thermal stability of nickel germanide using nitrogen plasma pretreatment for germanium-based technology. Sci China Inf Sci, 2018, 61: 109401 CrossRef Google Scholar
[14] Xu K, Cai Y H, Zhu W J. Esaki Diodes Based on 2-D/3-D Heterojunctions. IEEE Trans Electron Devices, 2018, 65: 4155-4159 CrossRef ADS Google Scholar
[15] McDonnell S, Addou R, Buie C. Defect-dominated doping and contact resistance in MoS2.. ACS Nano, 2014, 8: 2880-2888 CrossRef PubMed Google Scholar
[16] Schlaf R, Lang O, Pettenkofer C. Band lineup of layered semiconductor heterointerfaces prepared by van der Waals epitaxy: Charge transfer correction term for the electron affinity rule. J Appl Phys, 1999, 85: 2732-2753 CrossRef ADS Google Scholar
[17] Fang N, Nagashio K. Accumulation-Mode Two-Dimensional Field-Effect Transistor: Operation Mechanism and Thickness Scaling Rule. ACS Appl Mater Interfaces, 2018, 10: 32355-32364 CrossRef Google Scholar
[18] Jin Y, Keum D H, An S J. A Van Der Waals Homojunction: Ideal p-n Diode Behavior in MoSe2.. Adv Mater, 2015, 27: 5534-5540 CrossRef PubMed Google Scholar
[19] Doan M H, Jin Y, Adhikari S. Charge transport in MoS$_2$/WSe$_2$ van der Waals heterostructure with tunable inversion layer. ACS Nano, 2017, 11: 3832-3840 CrossRef Google Scholar
[20] Bludau W, Onton A, Heinke W. Temperature dependence of the band gap of silicon. J Appl Phys, 1974, 45: 1846-1848 CrossRef ADS Google Scholar
[21] Burton L A, Whittles T J, Hesp D. Electronic and optical properties of single crystal SnS$_2$: an earth-abundant disulfide photocatalyst. J Mater Chem A, 2016, 4: 1312-1318 CrossRef Google Scholar
[22] Huang Q Q, Huang R, Zhan Z, et al. A novel Si Tunnel FET with 36 mV/dec subthreshold slope based on junction depleted-modulation through striped Gate configuration. In: Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco, 2012. 187--190. Google Scholar
Figure 1
(Color online) (a) Schematic view of the vertical 2D/3D tunnel diode. Vertical tunneling occurs across the overlap region between the 2D material and the 3D material. (b) Top view of the vertical 2D/3D tunnel diode.
Figure 2
(Color online) The band diagram of the N$^+$ SnS$_2$/P$^+$ Si tunnel diode. (a) The bandgaps and electronic affinities of Si and SnS$_2$; (b) the equilibrium state; (c) the working state-reverse bias region.
Figure 3
(Color online) The details of the process to fabricate the vertical N$^+$ SnS$_2$/P$^+$ Si tunnel diode. (a) The original Si substrate; (b) ion implantation with BF$_2$$^+$; (c) highly p-doped Si; (d) dry etching to form trenches; (e) CVD of SiO$_2$; (f) CMP of SiO$_2$; (g) HF treatment to remove the residual and native oxide; (h) transfer of SnS$_2$ sheet; (i) formation of contacts.
Figure 4
(Color online) (a) The optical microscope image of the fabricated vertical N$^+$ SnS$_2$/P$^+$ Si tunnel diode; protectłinebreak (b) AFM image of fabricated vertical N$^+$ SnS$_2$/P$^+$ Si tunnel diode; (c) Raman characterization of the SnS$_2$ sheet in the tunnel diode.
Figure 5
(Color online) The electric characteristics of the vertical N$^+$ SnS$_2$/P$^+$ Si tunnel diode. (a) Linear and (b) log current-voltage characteristics.
Figure 6
(Color online) The NDR characteristic of the vertical N$^+$ SnS$_2$/P$^+$ Si tunnel diode. (a) The band diagram in the small forward bias region; (b) the band diagram in the large forward bias region.
Figure 7
(Color online) The temperature characteristic of the vertical N$^+$ SnS$_2$/P$^+$ Si tunnel diode.