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This work was supported by National Key Research and Development Program of China (Grant Nos. 2018YFB1306600, 2018YFB1306604), National Natural Science Foundation of China (Grant Nos. 61672436, 61601376, 61976246), and Fundamental Research Funds for the Provincial Universities (Grant No. GK199900299012-010).
Appendixes A–E.
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Figure 1
(Color online) (a) Schematic circuit diagram for stateful logic operations; (b) full adder.