SCIENCE CHINA Information Sciences, Volume 63 , Issue 10 : 209402(2020) https://doi.org/10.1007/s11432-019-2658-x

Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors

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  • ReceivedApr 7, 2019
  • AcceptedSep 19, 2019
  • PublishedMay 20, 2020


There is no abstract available for this article.


This work was supported in part by National Key Research and Development Plan (Grant No. 2016YFA0200504), National Science and Technology Major Project (Grant No. 2017ZX02315001-004), Program of National Natural Science Foundation of China (Grant Nos. 61421005, 61774012, 61574010), Beijing Innovation Center for Future Chips Foundation (Grant No. KYJJ2016008), and the 111 Project (Grant No. B18001).


[1] Bangsaruntip S, Cohen G M, Majumdar A, et al. High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling. In: Proceedings of 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, 2009. 1--4. Google Scholar

[2] Li M, Yeo K H, Suk S D, et al. Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate. In: Proceedings of 2009 Symposium on VLSI Technology, Honolulu, 2009. 94--95. Google Scholar

[3] Mertens H, Ritzenthaler R, Hikavyy A, et al. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates. In: Proceedings of IEEE Symposium on VLSI Technology, Honolulu, 2016. 1--2. Google Scholar

[4] Zhang Z, Jiang X, Wang R. Extraction of Process Variation Parameters in FinFET Technology Based on Compact Modeling and Characterization. IEEE Trans Electron Devices, 2018, 65: 847-854 CrossRef Google Scholar

[5] Iwai H, Natori K, Shiraishi K. Si nanowire FET and its modeling. Sci China Inf Sci, 2011, 54: 1004-1011 CrossRef Google Scholar

[6] Zhuge J, Wang R S, Huang R, et al. Experimental investigation and design optimization guidelines of characteristic variability in silicon nanowire CMOS technology. In: Proceedings of 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, 2009. 1--4. Google Scholar

[7] Jing Zhuge , Yu Tian , Runsheng Wang . High-Performance Si Nanowire Transistors on Fully Si Bulk Substrate From Top-Down Approach: Simulation and Fabrication. IEEE Trans Nanotechnol, 2010, 9: 114-122 CrossRef Google Scholar

[8] Liu Z H, Hu C, Huang J H. Threshold voltage model for deep-submicrometer MOSFETs. IEEE Trans Electron Devices, 1993, 40: 86-95 CrossRef Google Scholar

[9] Auth C P, Plummer J D. Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's. IEEE Electron Device Lett, 1997, 18: 74-76 CrossRef Google Scholar

  • Figure 1

    (Color online) (a) The cross section view of GAA SNWTs with non ideal structure ($l_1~\neq~l_2$); (b) comparison of the $I_{\rm~D}$-$V_{\rm~G}$ characteristics of GAA SNWTs with symmetrical and asymmetrical gate structure; (c) the unfolded drawing of the asymmetrical gate cut $l_2$ to form two cosine shaped gate edges; (d) the effective gate length changes with $l_2$ when $l_1$ is constant; (e) comparison of $I_{\rm~D}$-$V_{\rm~G}$ characteristics between the asymmetrical GAA SNWT and the equivalently symmetrical device; (f) the relative change of $L_{\rm~eff}$ to $l_1$ compared to the change of $l_2$.