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SCIENCE CHINA Information Sciences, Volume 64 , Issue 9 : 199103(2021) https://doi.org/10.1007/s11432-018-9648-x

Hashing multiple messages with SM3 on GPU platforms

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  • ReceivedJun 30, 2018
  • AcceptedNov 12, 2018
  • PublishedMar 16, 2021

Abstract

There is no abstract available for this article.


Acknowledgment

This work was supported in part by National Natural Science Foundation of China (Grant Nos. 61632020, 61472416, 61772520, 61602468, 61802392) and Key Research Project of Zhejiang Province (Grant No. 2017C01062).


Supplement

Appendixes A–D.


References

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[3] Ao T Y, He Z Q, Dai K, et al. A compact hardware implementation of SM3. In: Proceedings of the 13th International Conference on Trust, Security and Privacy in Computing and Communications, 2014. Google Scholar

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  • Table 1  

    Table 1Performance comparison with related work

    Data type Implementation Platform Latency (ms) Throughput (Gbps)
    Fixed lengthSM3 ([6]) ASIC 6.54
    Keccak-256 ([7]) GTX 295 17.70
    Plain-SM3GTX 1080 3.38 39.71
    TITAN Xp 2.52 53.26
    Optimized-SM3GTX 1080 395.59 86.86
    TITAN Xp 832.17 82.58
    Arbitrary lengthPlain-SM3GTX 1080 632.83 3.26
    TITAN Xp 525.26 3.92
    Optimized-SM3GTX 1080 298.45 6.90
    TITAN Xp 312.87 6.59
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