SCIENCE CHINA Information Sciences, Volume 62 , Issue 2 : 022401(2019) https://doi.org/10.1007/s11432-018-9555-8

Efficient evaluation model including interconnect resistance effect for large scale RRAM crossbar array matrix computing

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  • ReceivedMar 24, 2018
  • AcceptedAug 23, 2018
  • PublishedDec 28, 2018



This work was supported by National Natural Science Foundation of China (Grant Nos. 61334007, 61421005), and Shenzhen Science and Technology Innovation Committee (Grant No. JCYJ2017041215- 0411676).


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  • Figure 1

    (Color online) Computation deviation of the connection matrix method vs. array size ($n~\times~n$) at different tech nodes.

  • Figure 4

    (a) Equivalent circuit diagram of row (word line) $k$; (b) simplified circuit diagram of row $k$.

  • Figure 5

    (Color online) Voltage distribution at word lines with (a) uniform and (b) random cell resistance distribution.

  • Figure 6

    (Color online) Voltage and computation deviation rate at the nearest/farthest output with the (a) uniform and (b) random cell resistance distribution of the three methods vs. the crossbar array size at the 14 nm tech node.

  • Figure 7

    (Color online) Computation time of three methods with different crossbar array sizes ($n~\times~n$).

  • Figure 10

    (Color online) Voltage at the farthest output vs. HRS ratio with different nonlinearities. The array size is set to 64 $\times$ 64.

  • Table 1   Simulation parameters used for model validation
    Parameter Value
    Interconnect resistance ($R_{\rm~wire}$) 10.88 $\Omega$
    Low resistance state ($R_{\rm~on}$) 10 k$\Omega$
    Load resistance ($R_s$) 5 k$\Omega$
    Input voltage amplitude 1 V
    Resistance ratio ($R_{\rm~on}/R_{\rm~off}$) 1000