SCIENCE CHINA Information Sciences, Volume 62 , Issue 6 : 069402(2019) https://doi.org/10.1007/s11432-017-9549-8

Dependency of well-contact density on MCUs in 65-nm bulk CMOS SRAM

More info
  • ReceivedNov 12, 2017
  • AcceptedAug 14, 2018
  • PublishedOct 22, 2018


There is no abstract available for this article.


This work was supported by Preliminary Research Program of National University of Defense Technology of China (Grant No. 0100066314001).


[1] Chen J J, Liang B, Chi Y Q. Experimental characterization of the bipolar effect on P-hit single-event transients in 65 nm twin-well and triple-well CMOS technologies. Sci China Technol Sci, 2016, 59: 488-493 CrossRef Google Scholar

[2] Chatterjee I, Narasimham B, Mahatme N N. Impact of technology scaling on SRAM soft error rates. IEEE Trans Nucl Sci, 2014, 61: 3512-3518 CrossRef ADS Google Scholar

[3] Luo Y H, Zhang F Q, Guo H X. Single-event cluster multibit upsets due to localized latch-up in a 90 nm COTS SRAM containing SEL mitigation design. IEEE Trans Nucl Sci, 2014, 61: 1918-1923 CrossRef ADS Google Scholar

[4] Zhang K Y, Kobayashi K. Contributions of charge sharing andbipolar effects to cause or suppress MCUs on redundant latches. In: Proceedings of IEEE International Reliability Physics Symposium, 2013. Google Scholar

[5] Jeon S H, Lee S, Baeg S. Novel error detection scheme with the harmonious use of parity codes, well-taps, and interleaving distance. IEEE Trans Nucl Sci, 2014, 61: 2711-2717 CrossRef ADS Google Scholar

[6] Ibe E, Chung S S, Wen S J, et al. Spreading diversity in multi-cell neutron-induced upsets with device scaling. In: Proceedings of IEEE Custom Integrated Circuits Conference, 2006. 437--444. Google Scholar

[7] Gasiot G, Roche P, Flatresse P. Comparison of multiple cell upset response of bulk and SOI 130 nm technologies in the terrestrial environment. In: Proceedings of IEEE International Reliability Physics Symposium, 2008. Google Scholar

  • Figure 1

    (Color online) (a) Upset in logical word of SRAM in the experiments. The size of upset in physical address on three SRAMs in the experiments at O exposure (b), at Ti exposure (c), and at Ge exposure (d).