This work was supported by National Basic Research Program of China (973) (Grant No. 2015CB351906), National Natural Science Foundation of China (Grant No. 61774114), Shaanxi Province Science Foundation for Distinguished Young Scholars 2018, and 111 Project (Grant No. B12026).
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Figure 1
Stretchable-interconnect research.
Figure 2
Stretchable-interconnect-simulation flow.
Figure 3
Single stretchable interconnect.
Figure 4
Multiple-stretchable-interconnect series circuit.
Figure 5
(Color online) Delay simulation results. (a)
Figure 6
Multiple-stretchable-interconnect series circuit.
Figure 7
(Color online) The delays of the multiple-stretchable-interconnect series circuit with various applied strains at 10 GHz.
Figure 8
Coupled-stretchable-interconnect structure and port-definition diagram.
Figure 9
(Color online) (a) Near-end crosstalk; (b) far-end crosstalk.
Figure 10
Simulation circuit of coupled stretchable interconnects.
Figure 11
(Color online) Crosstalk of coupled stretchable interconnects at different frequencies. (a)
Figure 12
(Color online) Crosstalk of coupled stretchable interconnects with different applied strains. (a) Near-end crosstalk; (b) far-end crosstalk.
Figure 13
Flexible-passive-device simulation flow.
Figure 14
(Color online) Flexible capacitor: (a) capacitor electronic photograph; (b) two-dimensional layer in Cadence; (c) capacitor-reconstruction structure in ANSYS Q3D Extractor.
Figure 15
(Color online) Flexible resistance. (a) Resistor electronic photographs; (b) two-dimensional layers in Cadence; (c) resistor reconstruction in the ANSYS Q3D Extractor.
Figure 16
Flexible-active-device-simulation flow.
Figure 17
(Color online) NMOSFET device: (a) silicon structure, (b) PDMS substrate. PMOSFET device: (c) silicon structure, (d) PDMS substrate.
Figure 18
(Color online) (a) The variation of threshold voltage ${{\textit{V}_{\rm~th}}}$, transconductance ${{\textit{G}_{m}}}$, and on-resistance ${{\textit{R}_{\rm~on}}}$ with substrate thickness; (b) the relationship between gate capacitance and gate voltage.
Figure 19
Gate capacitance at the cut-off area.
Figure 20
Flexible-electronic-system simulation flow.
Figure 21
(Color online) (a) Latch-comparator circuit; (b) comparator verification circuit in the advanced design system.
Figure 22
(Color online) (a) Flexible-comparator-simulation results; (b) comparator circuit produces glitches.
Figure 23
Flexible-circuit-layout-wiring-simulation flow.
Figure 24
(Color online) The amplifier circuit's layout and wiring: the straight layout wiring diagram (a) in Cadence and (b) in the ANSYS Q3D Extractor; the stretchable-layout-wiring diagram (c) in Cadence and (d) in the ANSYS Q3D Extractor.
Figure 25
(Color online) Amplifier input and output waveforms (a) at 10 MHz and (b) at 100 MHz for the straight-wire-amplifier circuit; (c) at 10 MHz and (d) at 100 MHz for the stretchable-flexible-interconnect-amplifier circuit.
Figure 26
(Color online) Output waveform of the stretchable flexible interconnect amplifier under various applied strains.
| Device | Effective length | Effective width | Effective thickness | Effective spacing | Thickness |
| ($\mu$m) | ($\mu$m) | ($\mu$m) | ($\mu$m) | (mm) | |
| 10 $\mu$m $\times$ 10 $\mu$m | 10 | 10 | 0.048 | 0.048 | 1 |
| 20 $\mu$m $\times$ 20 $\mu$m | 20 | 20 | 0.048 | 0.048 | 1 |
| 30 $\mu$m $\times$ 30 $\mu$m | 30 | 30 | 0.048 | 0.048 | 1 |
| Device specification | Huahong NEC CD350G-60V80V capmip (fF) | Capacitance in the paper (fF) |
| 10 $\mu$m $\times$ 10 $\mu$m | 69.2 | 70.843 |
| 20 $\mu$m $\times$ 20 $\mu$m | 274.4 | 283.361 |
| 30 $\mu$m $\times$ 30 $\mu$m | 615.6 | 627.573 |
| Device specification ($\mu$m) | Huahong NEC CD350G-60V80V rplcd ($\Omega$) | Resistance in the paper ($\Omega$) |
| $L$ = 9.2 | 41.2371 | 41.7918 |
| $L$ = 17.2 | 82.4742 | 83.02892 |
| $L$ = 25.2 | 123.111 | 124.342 |
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