SCIENCE CHINA Information Sciences, Volume 61 , Issue 6 : 062404(2018) https://doi.org/10.1007/s11432-017-9305-x

All-metal electrodes vertical gate-all-around device with self-catalyzed selective grown InAs NWs array

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  • ReceivedSep 29, 2017
  • AcceptedNov 23, 2017
  • PublishedApr 19, 2018



This work was supported by National Basic Research Program of China (Grant No. 2012CB932700(02, 01)), National Key Research and Development Plan (Grant No. 2016YFA0200802), and National Natural Science Foundation of China (Grant No. 61621061). We thank Dr. Tuanwei SHI and Dr. Mengqi FU for the valuable discussions, Mr. Jun XU and Dr. Xing LI for assistance in FIB.


[1] Thelander C, Rehnstedt C, Froberg L E. Development of a vertical wrap-gated InAs FET. IEEE Trans Electron Device, 2008, 55: 3030-3036 CrossRef ADS Google Scholar

[2] Schmid H, Borg B M, Moselund K, et al. III-V semiconductor nanowires for future devices. In: Proceedings of the Conference on Design, Automation and Test in Europe, Dresden, 2014. Google Scholar

[3] Jansson K, Lind E, Wernersson L E. Performance evaluation of III-V nanowire transistors. IEEE Trans Electron Device, 2012, 59: 2375-2382 CrossRef ADS Google Scholar

[4] International Technology Roadmap for Semiconductors (ITRS), 2015. http://www.itrs2.net/. Google Scholar

[5] Egard M, Johansson S, Johansson A C, et al. Vertical InAs nanowire wrap gate transistors with f(t) &. Google Scholar

[6] Johansson S, Memisevic E, Wernersson L E. High-frequency gate-all-around vertical InAs nanowire MOSFETs on Si substrates. IEEE Electron Device Lett, 2014, 35: 518-520 CrossRef ADS Google Scholar

[7] Berg M, Persson K M, Wu J. InAs nanowire MOSFETs in three-transistor configurations: single balanced RF down-conversion mixers.. Nanotechnology, 2014, 25: 485203 CrossRef PubMed Google Scholar

[8] Auth C P, Plummer J D. Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's. IEEE Electron Device Lett, 1997, 18: 74-76 CrossRef ADS Google Scholar

[9] Bao T H, Yakimets D, Ryckaert J, et al. Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5 nm and beyond technologies. In: Proceedings of European Solid State Device Research Conference (ESSDERC), Venice, 2014. 102--105. Google Scholar

[10] Karmalkar S, Maheswaran K R K, Gurugubelli V. Ambient field effects on the current-voltage characteristics of nanowire field effect transistors. Appl Phys Lett, 2011, 98: 063508 CrossRef ADS Google Scholar

[11] Dayeh S A. Electron transport in indium arsenide nanowires. Semicond Sci Technol, 2010, 25: 024004 CrossRef ADS Google Scholar

[12] Dayeh S A, Aplin D P R, Zhou X. High electron mobility InAs nanowire field-effect transistors. Small, 2007, 3: 326-332 CrossRef PubMed Google Scholar

[13] Ford A C, Ho J C, Chueh Y L. Diameter-dependent electron mobility of InAs nanowires. Nano Lett, 2009, 9: 360-365 CrossRef PubMed ADS arXiv Google Scholar

[14] Sourribes M J L, Isakov I, Panfilova M. Minimization of the contact resistance between InAs nanowires and metallic contacts. Nanotechnology, 2013, 24: 045703 CrossRef PubMed ADS Google Scholar

[15] Shi T, Fu M, Pan D. Contact properties of field-effect transistors based on indium arsenide nanowires thinner than 16 nm. Nanotechnology, 2015, 26: 175202 CrossRef PubMed ADS Google Scholar

[16] Wernersson L E, Bryllert T, Lind E, et al. Wrap-gated InAs nanowire field-effect transistor. In: Proceedings of International Electron Devices Meeting (IEDM), Washington, 2005. 265--268. Google Scholar

[17] Tomioka K, Yoshimura M, Fukui T. A III-V nanowire channel on silicon for high-performance vertical transistors. Nature, 2012, 488: 189-192 CrossRef PubMed ADS Google Scholar

[18] Berg M, Persson K M, Kilpi O P, et al. Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si. In: Proceedings of International Electron Devices Meeting (IEDM), Washington, 2015. Google Scholar

[19] Tanaka T, Tomioka K, Hara S. Vertical surrounding gate transistors using single InAs nanowires grown on Si substrates. Appl Phys Express, 2010, 3: 025003 CrossRef ADS Google Scholar

[20] Fr$\rm~~\ddot{o}$berg L. Growth, physics, and device applications of InAs-based nanowires. Dissertation for Ph.D. Degree. Lund: Lund University, 2008. Google Scholar

[21] Wang X, Du W, Yang X. Self-catalyzed growth mechanism of InAs nanowires and growth of InAs/GaSb heterostructured nanowires on Si substrates. J Cryst Growth, 2015, 426: 287-292 CrossRef ADS Google Scholar

[22] Tomioka K, Tanaka T, Hara S. III-V nanowires on Si substrate: selective-area growth and device applications. IEEE J Sel Top Quantum Electron, 2011, 17: 1112-1129 CrossRef Google Scholar

[23] Shi T, Wang X, Wang B. Nanoscale opening fabrication on Si (111) surface from SiO$_{2}$ barrier for vertical growth of III-V nanowire arrays. Nanotechnology, 2015, 26: 265302 CrossRef PubMed ADS Google Scholar

[24] Mandl B, Stangl J, Hilner E. Growth mechanism of self-catalyzed group III-V nanowires. Nano Lett, 2010, 10: 4443-4449 CrossRef PubMed ADS Google Scholar

[25] Zhang Z Y, Jin C H, Liang X L. Current-voltage characteristics and parameter retrieval of semiconducting nanowires. Appl Phys Lett, 2006, 88: 073102 CrossRef ADS Google Scholar

[26] Fu M, Pan D, Yang Y. Electrical characteristics of field-effect transistors based on indium arsenide nanowire thinner than 10 nm. Appl Phys Lett, 2014, 105: 143101 CrossRef ADS Google Scholar

[27] Johansson S, Ghalamestani S G, Egard M. High frequency vertical InAs nanowire MOSFETs integrated on Si substrates. Phys Status Solidi C, 2012, 9: 350-353 CrossRef ADS Google Scholar

  • Figure 1

    (a) SEM image of one InAs NWs array (tilted at 30$^\circ$); (b) a high magnification SEM image of InAs NWs (tilted at 30$^\circ$); (c) a high-resolution TEM image of one typical InAs NW, the arrow points the growing direction.

  • Figure 2

    Schematic diagrams showing the fabrication process of VGAA FETs. (a) The self-catalyzed NWs array; (b) the sample after depositing the bottom metal (Ti/Al/W) and defining the bottom electrode; (c) the sample after defining the height of the bottom electrode with S1813; (d) the sample after removing the metal on the NWs using RIE and wet etching; (e) the sample after fabricating the spacer layer between the bottom and gate electrodes; (f) the sample after depositing $\rm~HfO_2$ layer using ALD; (g) the sample after depositing and definiting the gate electrode; (h) the sample after fabricating the spacer layer between the gate and top electrodes; (i) the sample after removing the $\rm~HfO_2$ on the top part of InAs NWs; (j) the sample after defining vias and removing the gate oxide in the vias; (k) the sample after depositing the top metal layer; (l) the sample after separating the three electrodes and finishing the fabrication of the VGAA FETs.

  • Figure 3

    (a) SEM image of the sample after fabricating the bottom electrodes; (b) SEM image of the sample after depositing the gate metal; (c) SEM image of one VGAA FET; (d) SEM image of VGAA FETs array; (e) the schematic diagrams of the cross sectional structure of a VGAA device (top diagram) and the equivalent circuit of the center part of a device (bottom diagram); (f) the cross sectional SEM of a VGAA device marked by fake colors. Only one NW in the device is shown to be clear. The left two images are the enlarged images of the areas outlined in the main image.

  • Figure 4

    (Color online) (a) The output curves and (b) the transfer curve of a typical VGAA FET.

  • Figure 5

    (Color online) Comparison of the electrical performance of the same VGAA FET before and after annealing.protect łinebreak (a) The output curves before annealing; (b) the output curves after annealing; (c) the transfer curve before annealing. The inset is the same curve in logarithmic coordinate; (d) the transfer curve after annealing.

  • Figure 6

    (Color online) (a) The output curves of a typical planar MOSFET based on single InAs NW with large diameter, and the insert is the SEM image of the same device; (b) the transfer curve of the same device in (a).