SCIENCE CHINA Information Sciences, Volume 61 , Issue 6 : 062401(2018) https://doi.org/10.1007/s11432-016-9106-x

Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate

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  • ReceivedDec 13, 2016
  • AcceptedMay 4, 2017
  • PublishedNov 20, 2017



This work was supported by National Natural Science Foundation of China (Grant Nos. 61404005, 61674008, 61421005) and National High Technology Research and Development Program of China (863) (Grant No. 2015AA016501).


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  • Figure 1

    (Color online) Schematic structure of the 14 nm Ge p-channel FinFET. The structure parameters are listed in Table 1.

  • Figure 2

    (Color online) Cross-sectional views at Planes 1 and 2. The definitions of the structure parameters are presented.

  • Figure 5

    (Color online) Spatial temperature distributions of the Ge p-channel single-fin 14 nm FinFET in Plane 1 at different gate voltages. Here $V_d$ is $-$0.63 V. (a) $V_g=-0.35$ V; (b) $V_g=-0.5$ V; (c) $V_g=-0.63$ V.

  • Figure 8

    (Color online) Hole temperature distributions (a)–(c) and lattice temperature distributions (d)–(f) in the Ge FinFETs with three different $L_{\rm~sdext}$s 10, 20, 40 nm from left to the right, where the input powers are all 60 ${\rm~\mu~W}$.

  • Figure 15

    (Color online) Variation tendency of the thermal resistances in multi-fin FinFETs with different fin numbers. Different fin pitches are compared.

  • Table 1   Structure parameters of the simulated FinFET
    Structure parameter Value
    Raised S/D height, $H_{\rm~sd}$ 52 nm
    Stop layer height, $H_{\rm~stop}$ 40 nm
    Substrate layer height, $H_{\rm~sub}$ 40 nm
    Fin height, $H_{\rm~fin}$ 42 nm
    Raised S/D length,$L_{\rm~sd}$ 20 nm
    S/D extension length, $L_{\rm~sdext}$ 20 nm
    Gate length, $L_{g}$ 20 nm
    Pitch, $W_{\rm~pitch}$ 47 nm
    Fin width, $W_{\rm~fin}$ 7 nm
    Channel doping, $n$ type 1$\times{\rm~10^{15}cm^{-3}}$
    Stop layer doping, $n$ type 1$\times{\rm~10^{18}cm^{-3}}$
    Source/drain doping, $p$ type 2$\times{\rm~10^{19}cm^{-3}}$
    Gate oxide thickness (EOT) 0.68 nm
  • Table 2   Mobility model parameters $^{\rm~a)}$
    Parameter Unit Hole Parameter Unit Hole
    Arora ModelExtended Canali Model
    $A_{\rm~min}$ ${\rm~cm^2/Vs}$ 1900 $\nu_{\rm~sat}$ cm/s 1.4$\times10^7$
    $\alpha_m$ 1 $-$2.3 $\beta_{\rm~exp}$ ${\rm~cm^{5/3}V^{-2/3}s^{-1}}$ 0.17
    Enhanced Lombardi Model
    B cm/s 1.993$\times10^5$ A 1 1.5
    C ${\rm~cm^{5/3}V^{-2/3}s^{-1}}$ 4875 $\alpha_\bot$ ${\rm~cm^3}$ 0
    $N_0$ ${\rm~cm^{-3}}$ 1 $N_l$ ${\rm~cm^{-3}}$ 1
    $N_2$ ${\rm~cm^{-3}}$ 1 $\nu$ 1 1
    $\lambda$ 1 0.0317 $\eta$ ${\rm~V^{2}cm^{-1}s^{-1}}$ $2.0546\times~10^{30}$
    k 1 1 $a_{\rm~other}$ 1 0
    $\delta$ ${\rm~cm^2/Vs}$ $1.705\times~10^{11}$ $l_{\rm~crit}$ cm $1\times~10^{-7}$

    a) Other mobility parameters not listed here are default values in Sentaurus [21].