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SCIENCE CHINA Information Sciences, Volume 59 , Issue 6 : 061401(2016) https://doi.org/10.1007/s11432-016-5567-z

Looking into the future of Nanoelectronics in the Diversification Efficient Era

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  • ReceivedNov 24, 2015
  • AcceptedDec 22, 2015
  • PublishedMay 11, 2016

Abstract


Acknowledgment

Acknowledgments

This work was supported by Nano 2017 CEA, LETI/STMicroelectronics/IBM Alliance Program, CEA/SOITEC Joint Program, Multiple Eureka and EU FP7 Projects, CEA ZeroPOVA and A3DN Flagship Programs.


References

[1] Fettweis G, Zimmermann E. ICT energy consumption---trends and challenges. In: Proceedings of 11th International Symposium on Wireless Personal Multimedia Communications, Dresden, 2008. 1--6. Google Scholar

[2] Reller A. Phys Status Solidi, 2011, 5: 309-311 Google Scholar

[3] Van Belle G. Statistical Rules of Thumb. 2nd ed. Hoboken: Wiley-Interscience, 2008. 99. Google Scholar

[4] Faynot O, Andrieu F, Weber O, et al. Planar fully depleted SOI technology: a powerful architecture for the 20nm node and beyond. In: Proceedings of 2010 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2010. 3.2.1--3.2.4. Google Scholar

[5] Weber O, Josse E, Andrieu F, et al. 14nm FDSOI technology for high speed and energy efficient applications. In: Digest of Technical Papers of 2014 Symposium on VLSI Technology (VLSI-Technology), Honolulu, 2014. 1--2. Google Scholar

[6] Weber O, Josse E, Mazurier J, et al. 14nm FDSOI upgraded device performance for ultra-low voltage operation. In: Proceedings of 2015 Symposium on VLSI Technology (VLSI Technology), Kyoto, 2015. 168--169. Google Scholar

[7] Ventosa C, Morales C, Libralesso L, et al. Electrochem Solid-State Lett, 2009, 12: H373-H375 Google Scholar

[8] Deleonibus S, Faynot O, Ernst T, et al. Future challenges and opportunities for heterogeneous process technology. Towards the thin films, zero intrinsic variability devices, zero power era. In: Proceedings of 2014 IEEE International Electron Devices Meeting, San Francisco, 2014. 9.2.1--9.2.4. Google Scholar

[9] Weber O, Faynot O, Andrieu F, et al. High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding. In: Proceedings of 2008 IEEE International Electron Devices Meeting, San Francisco, 2008. 1--4. Google Scholar

[10] Barraud S, Coquand R, Maffini-Alvaro V, et al. Scaling of $\Omega$-gate SOI nanowire N- and P-FET down to 10nm gate length: size- and orientation-dependent strain effects. In: Proceedings of 2013 Symposium on VLSI Technology (VLSIT), Kyoto, 2013. T230--T231. Google Scholar

[11] Deleonibus S. Intelligent Integrated Systems. Vol 1. Singapore: Pan Stanford Publishing Corp., 2014. Google Scholar

[12] Ernst T, Duraffourg L, Dupré C, et al. Novel Si-based nanowire devices: will they serve ultimate MOSFETs scaling or ultimate hybrid integration? In: Proceedings of 2008 IEEE International Electron Devices Meeting, San Francisco, 2008. 1--4. Google Scholar

[13] Coquand R, Casse M, Barraud S, et al. Strain-induced performance enhancement of tri-gate and $\Omega$-gate nanowire FETs scaled down to 10nm width. In: Proceedings of 2012 Symposium on VLSI Technology (VLSIT), Honolulu, 2012. 13--14. Google Scholar

[14] Carron V, Nemouchi F, Milesi F, et al. Thermal stability enhancement of Ni-based silicides, germano-silicides and germanides using W and F implantation for 3D CMOS sequential integration. In: Proceedings of 2014 International Workshop on Junction Technology (IWJT), Shanghai, 2014. 1--6. Google Scholar

[15] Hutin L, Vinet M, Poiroux T, et al. Dual metallic source and drain integration on planar single and double gate SOI CMOS down to 20nm: performance and scalability assessment. In: Proceedings of 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, 2009. 1--4. Google Scholar

[16] Vinet M, Poiroux T, Licitra C, et al. IEEE Electron Dev Lett, 2009, 30: 748-750 Google Scholar

[17] Wilson R, Beigne E, Flatresse P, et al. A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. In: Digest of Technical Papers of 2014 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2014. 452--453. Google Scholar

[18] Arcamone J, Philippe J, Arndt G, et al. monolithically integrated with CMOS: emerging applications and technologies. In: Proceedings of 2014 IEEE International Electron Devices Meeting, San Francisco, 2014. 22.1.1--22.1.4. Google Scholar

[19] Kita K, Toriumi A. Intrinsic origin of electric dipoles formed at high-k/SiO2 interface. In: Proceedings of 2008 IEEE International Electron Devices Meeting, San Francisco, 2008. 1--4. Google Scholar

[20] Gupta S, Manik P P, Mishra R K, et al. J Appl Phys, 2013, 113: 234505-750 Google Scholar

[21] Mayer F, Le Royer C, Damlencourt J F, et al. Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance. In: Proceedings of 2008 IEEE International Electron Devices Meeting, San Francisco, 2008. 1--5. Google Scholar

[22] Tomioka K, Yoshimura M, Nakai E, et al. Integration of III-V nanowires on Si: from high-performance vertical FET to steepslope switch. In: Proceedings of 2013 IEEE International Electron Devices Meeting, Washington DC, 2013. 4.4.1--4.4.4. Google Scholar

[23] Avci U E, Rios R, Kuhn K, et al. Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic. In: Proceedings of 2011 Symposium on VLSI Technology (VLSIT), Honolulu, 2011. 124--125. Google Scholar

[24] Villalon A, Le Royer C, Nguyen P, et al. First demonstration of strained SiGe nanowires TFETs with ION beyond 700$\upmu$A/$\upmu$m. In: Digest of Technical Papers of 2014 Symposium on VLSI Technology (VLSI-Technology), Honolulu, 2014. 1--2. Google Scholar

[25] International Technology Roadmap for Semiconductors (ITRS). Available at http://www.itrs2.net/. Google Scholar

[26] Molas G, Deleruyelle D, De Salvo B, et al. IEDM 2004, Impact of few electron phenomena on floating-gate memory reliability. In: Technical Digest of IEEE International Electron Devices Meeting, San Francisco, 2004. 877--880. Google Scholar

[27] Wacquez R, Vinet M, Pierre M, et al. Single dopant impact on electrical characteristics of SOI NMOSFETs with effective length down to 10nm. In: Proceedings of 2010 Symposium on VLSI Technology, Honolulu, 2010. 193--194. Google Scholar

[28] Vinet M, Deshpande V, Jehl X, et al. FDSOI nanowires: an opportunity for hybrid circuit with field effect and single electron transistors. In: Proceedings of 2013 IEEE International Electron Devices Meeting, Washington DC, 2013. 26.4.1--26.4.4. Google Scholar

[29] Roche B, Riwar R-P, Voisin B, et al. Nat Commun, 2013, 4: 1581-750 Google Scholar

[30] Shinada T, Hori M, Guagliardo F, et al. Quantum transport in deterministically implanted single-donors in Si FETs. In: Proceedings of 2011 IEEE International Electron Devices Meeting (IEDM), Washington DC, 2011. 30.4.1--30.4.4. Google Scholar

[31] Fuechsle M, Mahapatra S, Zwanenburg F A, et al. Nat Nanotech, 2010, 5: 502-505 Google Scholar

[32] Mathey L, Veyre L, Fontaine H, et al. Deterministic positioning of dopants on silicon wafers for ultimate processes. In: Proceedings of 217th meeting of the Electroch Society, Hawai, 2012. Google Scholar

[33] Ma N, Jena D. Phys Rev X, 2014, 4: 011043-505 Google Scholar

[34] Kim K S, Zhao Y, Jang H, et al. Nature, 2009, 457: 706-710 Google Scholar

[35] Mak K F, Lee C, Hone J, et al. Phys Rev Lett, 2010, 105: 136805-710 Google Scholar

[36] Lopez-Sanchez O, Llado E A, Koman V, et al. ACS Nano, 2014, 8: 3042-3048 Google Scholar

[37] Tiron R, Gharbi A, Argoud M, et al. Proc SPIE, 2013, 8680: 868012-3048 Google Scholar

[38] Posseme N, Pollet O, Barnola S. Appl Phys Lett, 2014, 105: 051605-3048 Google Scholar

[39] Dijon J, Okuno H, Fayolle M, et al. Ultra-high density carbon nanotubes on Al-Cu for advanced vias. In: Proceedings of 2010 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2010. 33.4.1--33.4.4. Google Scholar

[40] Barnola Clavé, Chatelain G, Filoramo A, et al. Org Biomol Chem, 2014, 12: 2778-2783 Google Scholar

[41] Suri M, Bichler O, Querlioz D, et al. CBRAM devices as binary synapses for low-power stochastic neuromorphic systems: auditory (Cochlea) and visual (Retina) cognitive processing applications. In: Proceedings of 2012 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2012. 10.3.1--10.3.4. Google Scholar

[42] Vianello E, Thomas O, Molas G, et al. Resistive memories for ultra-low-power embedded computing design. In: Proceedings of 2014 IEEE International Electron Devices Meeting, San Francisco, 2014. 6.3.1--6.3.4. Google Scholar

[43] Ghezzi G E, Morel R, Brenac A, et al. Appl Phys Lett, 2012, 101: 233113-2783 Google Scholar

[44] Lattard L. Maskless lithography for volume manufacturing. In: Proceedings of SEMICON Europa 2014, Grenoble, 2014. Google Scholar

[45] Houri S, Billiot G, Belleville M, et al. IEEE Trans Circuits Syst I-Regul Pap, 2015, 62: 1546-1554 Google Scholar

[46] Milaninia K M, Baldo M A, Reina A, et al. Appl Phys Lett, 2009, 95: 183105-1554 Google Scholar

[47] Sun J, Wang W Z, Muruganathan M, et al. Appl Phys Lett, 2014, 105: 033103-1554 Google Scholar

[48] Batude P, Vinet M, Previtali B, et al. Advances, challenges and opportunities in 3D CMOS sequential integration. In: Proceedings of 2011 IEEE International Electron Devices Meeting (IEDM), Washington DC, 2011. 7.3.1--7.3.4. Google Scholar

[49] Turkyilmaz O, Cibrario G, Rozeau O, et al. 3d FPGA using highdensity interconnect monolithic integration. In: Proceedings of 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2014. 1--4. Google Scholar

[50] Abe K, Tendulkar M P, Jameson J R, et al. Ultra-high Bandwidth Memory with 3D-stacked Emerging Memory Cells. In: Proceedings of 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, Austin, 2008. 203--206. Google Scholar

[51] Batude P, Fenouillet-Beranger C, Pasini L, et al. 3DVLSI with CoolCube process: an alternative path to scaling. In: Proceedings of 2015 Symposium on VLSI Technology (VLSI Technology), Kyoto, 2015. T48--T49. Google Scholar

[52] Poupon G, Lamy Y, Rouzaud A. New era for packaging and coming challenges for interposers. In: Pan Pacific Symposium Conference Proceedings, Hawaii, 2014. Google Scholar

[53] El Bouayadi O, Lamy Y, Dussopt L. A high-impedance surface antenna on silicon interposer for 3D integrated mmW transceivers. In: Proceedings of 44th European Microwave Conference (EuMC), Rome, 2014. 112--115. Google Scholar

[54] Phan V P, Pecquenard B, Le Cras F. Adv Funct Mater, 2012, 22: 2580-2584 Google Scholar

[55] Di Cioccio L, Baudin F, Gergaud P, et al. ECS Trans, 2014, 64: 339-355 Google Scholar