References
[1]
Semiconductor Industry Association Global Sales Report. http://www.semiconductors.org/industry{\_}statistics/global{\_}\linebreak sales{\_}report/.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Semiconductor Industry Association Global Sales Report. http://www.semiconductors.org/industry{\_}statistics/global{\_}\linebreak sales{\_}report/&
[2]
Moore
G E.
Electronics,
1965, 38: 82-85
Google Scholar
http://scholar.google.com/scholar_lookup?author=Moore G E&publication_year=1965&journal=Electronics&volume=38&pages=82-85
[3]
Auth C, Allen C, Blattner A, et al. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. In: Proceedings of VLSI 2012 Symposium on Technology (VLSIT), Honolulu, 2012. 131--132.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Auth C, Allen C, Blattner A, et al. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. In: Proceedings of VLSI 2012 Symposium on Technology (VLSIT), Honolulu, 2012. 131--132&
[4]
Dennard
R H,
Gaensslen
F H,
Rideout
V L, et al.
IEEE J Solid-State Circuits,
1974, 9: 256-268
Google Scholar
http://scholar.google.com/scholar_lookup?author=Dennard R H&author=Gaensslen F H&author=Rideout V L&publication_year=1974&journal=IEEE J Solid-State Circuits&volume=9&pages=256-268
[5]
Wann H, Ko P K, Hu C. Gate-induced band-to-band tunneling leakage current in LDD MOSFETs. In: Technical Digest of International Electron Devices Meeting, San Francisco, 1992. 147--150.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Wann H, Ko P K, Hu C. Gate-induced band-to-band tunneling leakage current in LDD MOSFETs. In: Technical Digest of International Electron Devices Meeting, San Francisco, 1992. 147--150&
[6]
Bhavnagarwala A, Kosonocky S, Radens C, et al. Fluctuation limits {&} scaling opportunities for CMOS SRAM cells. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2005. 659--662.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Bhavnagarwala A, Kosonocky S, Radens C, et al. Fluctuation limits {&} scaling opportunities for CMOS SRAM cells. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2005. 659--662&
[7]
Choi
Y-K,
Asano
K,
Lindert
N, et al.
IEEE Electron Dev Lett,
1999, 21: 254-255
Google Scholar
http://scholar.google.com/scholar_lookup?author=Choi Y-K&author=Asano K&author=Lindert N&publication_year=1999&journal=IEEE Electron Dev Lett&volume=21&pages=254-255
[8]
Noel J-P, Thomas O, Jaud M-A, et al. UTB-FDSOI device architecture dedicated to low power design techniques. {In: Proceedings of the European Solid-State Device Research Conference (ESSDERC)}, Sevilla, 2010. 210--213.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Noel J-P, Thomas O, Jaud M-A, et al. UTB-FDSOI device architecture dedicated to low power design techniques. {In: Proceedings of the European Solid-State Device Research Conference (ESSDERC)}, Sevilla, 2010. 210--213&
[9]
Tsutsui
G,
Saitoh
M,
Hiramoto
T.
IEEE Electron Dev Lett,
2005, 26: 836-838
Google Scholar
http://scholar.google.com/scholar_lookup?author=Tsutsui G&author=Saitoh M&author=Hiramoto T&publication_year=2005&journal=IEEE Electron Dev Lett&volume=26&pages=836-838
[10]
Skotnicki
T,
Hutchby
J A,
King
T-J, et al.
IEEE Circuits Dev Mag,
2006, 21: 16-26
Google Scholar
http://scholar.google.com/scholar_lookup?author=Skotnicki T&author=Hutchby J A&author=King T-J&publication_year=2006&journal=IEEE Circuits Dev Mag&volume=21&pages=16-26
[11]
Kilchytska
V,
Md
Arshad M K,
Makovejev
S, et al.
Solid-State Electron,
2012, 70: 50-58
Google Scholar
http://scholar.google.com/scholar_lookup?author=Kilchytska V&author=Md Arshad M K&author=Makovejev S&publication_year=2012&journal=Solid-State Electron&volume=70&pages=50-58
[12]
Fenouillet-Beranger C, Denormel S, Icard B, et al. Fully-depleted SOI technology using high-K and single-metal gate for 32nm node LSTP applications featuring 0.179$\upmu $m$^{2}$ 6T-SRAM bitcell. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2007. 267--270.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Fenouillet-Beranger C, Denormel S, Icard B, et al. Fully-depleted SOI technology using high-K and single-metal gate for 32nm node LSTP applications featuring 0.179$\upmu $m$^{2}$ 6T-SRAM bitcell. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2007. 267--270&
[13]
Skotnicki T. Competitive SOC with UTBB SOI. In: Proceedings of 2011 IEEE International SOI Conference (SOI), Tempe, 2011. 1--61.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Skotnicki T. Competitive SOC with UTBB SOI. In: Proceedings of 2011 IEEE International SOI Conference (SOI), Tempe, 2011. 1--61&
[14]
Liu Q, Yagashita A, Loubet N, et al. Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond. In: Proceedings of 2010 Symposium on VLSI Technology (VLSIT), Honolulu, 2010. 61--62.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Liu Q, Yagashita A, Loubet N, et al. Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond. In: Proceedings of 2010 Symposium on VLSI Technology (VLSIT), Honolulu, 2010. 61--62&
[15]
Grenouillet L, Vinet M, Gimbert J, et al. UTBB FDSOI transistors with dual STI and shrinked back gate architecture for a multi-$V_{T}$ strategy at 20nm node and below. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2012. 64--67.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Grenouillet L, Vinet M, Gimbert J, et al. UTBB FDSOI transistors with dual STI and shrinked back gate architecture for a multi-$V_{T}$ strategy at 20nm node and below. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2012. 64--67&
[16]
Andrieu F, Weber O, Mazurier J, et al. Low leakage and low variability ultra-thin body and buried oxide (UT2B) SOI technology for 20nm low power CMOS and beyond. In: Proceedings of 2010 Symposium on VLSI Technology (VLSIT), Honolulu, 2010. 57--58.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Andrieu F, Weber O, Mazurier J, et al. Low leakage and low variability ultra-thin body and buried oxide (UT2B) SOI technology for 20nm low power CMOS and beyond. In: Proceedings of 2010 Symposium on VLSI Technology (VLSIT), Honolulu, 2010. 57--58&
[17]
Numata T, Noguchi M, Oowaki Y, et al. Back gate engineering for suppression of threshold voltage fluctuation in fully-depleted SOI MOSFETs. In: Proceedings of 2000 IEEE International SOI Conference, Wakefield, 2000. 78--79.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Numata T, Noguchi M, Oowaki Y, et al. Back gate engineering for suppression of threshold voltage fluctuation in fully-depleted SOI MOSFETs. In: Proceedings of 2000 IEEE International SOI Conference, Wakefield, 2000. 78--79&
[18]
Sugii N, Tsuchiya R, Ishigaki T, et al. Comprehensive study on Vth variability in silicon on thin BOX (SOTB) CMOS with small random-dopant fluctuation: finding a way to further reduce variation. In: Proceedings of 2008 International Electron Devices Meeting, San Francisco, 2008. 1--4.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Sugii N, Tsuchiya R, Ishigaki T, et al. Comprehensive study on Vth variability in silicon on thin BOX (SOTB) CMOS with small random-dopant fluctuation: finding a way to further reduce variation. In: Proceedings of 2008 International Electron Devices Meeting, San Francisco, 2008. 1--4&
[19]
Sugii
N,
Tsuchiya
R,
Ishigaki
T, et al.
IEEE Trans Electron Dev,
2010, 57: 835-845
Google Scholar
http://scholar.google.com/scholar_lookup?author=Sugii N&author=Tsuchiya R&author=Ishigaki T&publication_year=2010&journal=IEEE Trans Electron Dev&volume=57&pages=835-845
[20]
Doris B, Ieong M, Zhu T, et al. Device design considerations for ultra-thin SOI MOSFETs. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2003. 27.3.1--27.3.4.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Doris B, Ieong M, Zhu T, et al. Device design considerations for ultra-thin SOI MOSFETs. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2003. 27.3.1--27.3.4&
[21]
Schwarzenbach W, Cauchy X, Boedt F, et al. Excellent silicon thickness uniformity on ultra-thin SOI for controlling $V_{T}$ variation of FDSOI. In: Proceedings of IEEE International Conference on IC Design and Technology, Kao-hsiung, 2011. 1--3.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Schwarzenbach W, Cauchy X, Boedt F, et al. Excellent silicon thickness uniformity on ultra-thin SOI for controlling $V_{T}$ variation of FDSOI. In: Proceedings of IEEE International Conference on IC Design and Technology, Kao-hsiung, 2011. 1--3&
[22]
Nayfeh
H M,
Singh
D V,
Hergenrother
J M, et al.
IEEE Electron Dev Lett,
2006, 27: 288-290
Google Scholar
http://scholar.google.com/scholar_lookup?author=Nayfeh H M&author=Singh D V&author=Hergenrother J M&publication_year=2006&journal=IEEE Electron Dev Lett&volume=27&pages=288-290
[23]
Barral V, Poiroux T, Andrieu F, et al. Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO$_{2}$ gate stack. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2007. 61--64.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Barral V, Poiroux T, Andrieu F, et al. Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO$_{2}$ gate stack. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2007. 61--64&
[24]
Uchida K, Watanabe H, Kinoshita A, et al. Experimental study on carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2002. 47--50.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Uchida K, Watanabe H, Kinoshita A, et al. Experimental study on carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2002. 47--50&
[25]
Faynot O, Andrieu F, Weber O, et al. Planar fully depleted SOI technology: a powerful architecture for the 20nm node and beyond. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2010. 50--53.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Faynot O, Andrieu F, Weber O, et al. Planar fully depleted SOI technology: a powerful architecture for the 20nm node and beyond. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2010. 50--53&
[26]
Fenouillet-Beranger C, Perreau P, Pham-Nguyen L, et al. Hybrid FDSOI/Bulk high-k/Metal gate platform for Low Power (LP) multimedia technology. In: Technical Digest of International Electron Devices Meeting, Baltimore, 2009. 1--4.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Fenouillet-Beranger C, Perreau P, Pham-Nguyen L, et al. Hybrid FDSOI/Bulk high-k/Metal gate platform for Low Power (LP) multimedia technology. In: Technical Digest of International Electron Devices Meeting, Baltimore, 2009. 1--4&
[27]
Majumdar
A,
Wang
X,
Kumar
A, et al.
IEEE Electron Dev Lett,
2009, 30: 413-415
Google Scholar
http://scholar.google.com/scholar_lookup?author=Majumdar A&author=Wang X&author=Kumar A&publication_year=2009&journal=IEEE Electron Dev Lett&volume=30&pages=413-415
[28]
Majumdar
A,
Ren
Z,
Koester
S J, et al.
IEEE Trans Electron Dev,
2009, 56: 2270-2276
Google Scholar
http://scholar.google.com/scholar_lookup?author=Majumdar A&author=Ren Z&author=Koester S J&publication_year=2009&journal=IEEE Trans Electron Dev&volume=56&pages=2270-2276
[29]
Cheng K, Khakifirooz A, Kulkarni P, et al. Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain. In: Proceedings of 2009 Symposium on VLSI Technology (VLSIT), Honolulu, 2009. 212--213.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Cheng K, Khakifirooz A, Kulkarni P, et al. Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain. In: Proceedings of 2009 Symposium on VLSI Technology (VLSIT), Honolulu, 2009. 212--213&
[30]
Khakifirooz A, Cheng K, Nagumo T, et al. Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS. In: Proceedings of 2012 Symposium on VLSI Technology (VLSIT), Honolulu, 2012. 117--118.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Khakifirooz A, Cheng K, Nagumo T, et al. Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS. In: Proceedings of 2012 Symposium on VLSI Technology (VLSIT), Honolulu, 2012. 117--118&
[31]
Cheng K, Khakifirooz A, Kulkarni P, et al. Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. In: Proceedings of 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, 2009. 49--52.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Cheng K, Khakifirooz A, Kulkarni P, et al. Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. In: Proceedings of 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, 2009. 49--52&
[32]
Cheng K, Khakifirooz A, Loubet N, et al. High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained sige channel PFET. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2012. 18.1.1--18.4.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Cheng K, Khakifirooz A, Loubet N, et al. High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained sige channel PFET. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2012. 18.1.1--18.4&
[33]
Khakifirooz A, Cheng K, Kulkarni P, et al. Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications. In: Proceedings of International Symposium on VLSI Technology Systems and Applications (VLSI-TSA), Hsinchu, 2010. 110--111.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Khakifirooz A, Cheng K, Kulkarni P, et al. Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications. In: Proceedings of International Symposium on VLSI Technology Systems and Applications (VLSI-TSA), Hsinchu, 2010. 110--111&
[34]
Ponoth S, Vinet M, Grenouillet L, et al. Implant approaches and challenges for 20nm node and beyond ETSOI devices. In: Proceedings of 2011 IEEE International SOI Conference, Tempe, 2011. 1--2.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Ponoth S, Vinet M, Grenouillet L, et al. Implant approaches and challenges for 20nm node and beyond ETSOI devices. In: Proceedings of 2011 IEEE International SOI Conference, Tempe, 2011. 1--2&
[35]
Chau R, Kavalieros J, Doyle B, et al. A 50nm depleted-substrate CMOS Transistor (DST). In: Technical Digest of International Electron Devices Meeting, Washington DC, 2001. 29.1.1--29.1.4.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Chau R, Kavalieros J, Doyle B, et al. A 50nm depleted-substrate CMOS Transistor (DST). In: Technical Digest of International Electron Devices Meeting, Washington DC, 2001. 29.1.1--29.1.4&
[36]
Krivokapic Z, Maszara W, Arasnia F, et al. High performance 25nm FDSOI devices with extremely thin silicon channel. In: Proceedings of 2003 Symposium on VLSI Technology (VLSIT), Kyoto, 2003, 131--132.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Krivokapic Z, Maszara W, Arasnia F, et al. High performance 25nm FDSOI devices with extremely thin silicon channel. In: Proceedings of 2003 Symposium on VLSI Technology (VLSIT), Kyoto, 2003, 131--132&
[37]
Chen H, Chang C, Huang C, et al. Novel 20nm hybrid SOI/bulk CMOS technology with 0.183$\upmu$m$^{2}$ 6T-SRAM cell by immersion lithography. In: Proceedings of 2005 Symposium on VLSI Technology (VLSIT), Kyoto, 2005. 16--17.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Chen H, Chang C, Huang C, et al. Novel 20nm hybrid SOI/bulk CMOS technology with 0.183$\upmu$m$^{2}$ 6T-SRAM cell by immersion lithography. In: Proceedings of 2005 Symposium on VLSI Technology (VLSIT), Kyoto, 2005. 16--17&
[38]
Fenouillet C, Perreau P, Denorme S, et al. Impact of a 10 nm ultrathin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below. {In: Proceedings of the European Solid-State Device Research Conference (ESSDERC)}, Athens, 2009. 89--91.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Fenouillet C, Perreau P, Denorme S, et al. Impact of a 10 nm ultrathin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below. {In: Proceedings of the European Solid-State Device Research Conference (ESSDERC)}, Athens, 2009. 89--91&
[39]
Fenouillet C, Thomas O, Perreau P, et al. Efficient multi-$V_{T}$ FDSOI technology with UTBOX for low power circuit design. In: Proceedings of 2010 Symposium on VLSI Technology (VLSIT), Honolulu, 2010. 65--66.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Fenouillet C, Thomas O, Perreau P, et al. Efficient multi-$V_{T}$ FDSOI technology with UTBOX for low power circuit design. In: Proceedings of 2010 Symposium on VLSI Technology (VLSIT), Honolulu, 2010. 65--66&
[40]
Skotnicki
T,
Fenouillet-Beranger
C,
Gallon
C, et al.
IEEE Trans Electron Dev,
2008, 55: 96-130
Google Scholar
http://scholar.google.com/scholar_lookup?author=Skotnicki T&author=Fenouillet-Beranger C&author=Gallon C&publication_year=2008&journal=IEEE Trans Electron Dev&volume=55&pages=96-130
[41]
Leobandung E, Barth E, Sherony M, et al. High performance 0.18 pm SOI CMOS technology. In: Technical Digest of International Electron Devices Meeting, Washington DC, 1999. 679--682.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Leobandung E, Barth E, Sherony M, et al. High performance 0.18 pm SOI CMOS technology. In: Technical Digest of International Electron Devices Meeting, Washington DC, 1999. 679--682&
[42]
Puri R, Chuang C T. Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits. In: Proceedings of 1998 IEEE International SOI Conference, Stuart, 1998. 103--104.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Puri R, Chuang C T. Hysteresis effect in pass-transistor based partially-depleted SOI CMOS circuits. In: Proceedings of 1998 IEEE International SOI Conference, Stuart, 1998. 103--104&
[43]
Skotnicki
T,
Fenouillet-Beranger
C,
Gallon
C, et al.
IEEE Trans Electron Dev,
2008, 55: 96-130
Google Scholar
http://scholar.google.com/scholar_lookup?author=Skotnicki T&author=Fenouillet-Beranger C&author=Gallon C&publication_year=2008&journal=IEEE Trans Electron Dev&volume=55&pages=96-130
[44]
Khakifirooz
A,
Antoniadis
D A.
IEEE Trans Electron Dev,
2008, 55: 1391-1400
Google Scholar
http://scholar.google.com/scholar_lookup?author=Khakifirooz A&author=Antoniadis D A&publication_year=2008&journal=IEEE Trans Electron Dev&volume=55&pages=1391-1400
[45]
Pelgrom
M.
IEEE J Solid-State Circuits,
1989, 24: 1433-1439
Google Scholar
http://scholar.google.com/scholar_lookup?author=Pelgrom M&publication_year=1989&journal=IEEE J Solid-State Circuits&volume=24&pages=1433-1439
[46]
Cheng K, Khakifirooz A. FDSOI technology and its implications to analog and digital design. In: Jiang X C, ed. Digitally-Assisted Analog and Analog-Assisted Digital IC Design. Cambridge: Cambridge University Press, 2015. 86.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Cheng K, Khakifirooz A. FDSOI technology and its implications to analog and digital design. In: Jiang X C, ed. Digitally-Assisted Analog and Analog-Assisted Digital IC Design. Cambridge: Cambridge University Press, 2015. 86&
[47]
Kuhn
K J.
IEEE Trans Electron Dev,
2012, 59: 1813-1828
Google Scholar
http://scholar.google.com/scholar_lookup?author=Kuhn K J&publication_year=2012&journal=IEEE Trans Electron Dev&volume=59&pages=1813-1828
[48]
Yamamoto Y, Makiyama H, Shinohara H, et al. Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 V utilizing adaptive back bias. In: Proceedings of 2013 Symposium on VLSI Technology (VLSIT), Kyoto, 2013. T212--T213.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Yamamoto Y, Makiyama H, Shinohara H, et al. Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 V utilizing adaptive back bias. In: Proceedings of 2013 Symposium on VLSI Technology (VLSIT), Kyoto, 2013. T212--T213&
[49]
Khakifirooz A, Cheng K, Jagannathan B, et al. Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. In: 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, 2010. 152--153.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Khakifirooz A, Cheng K, Jagannathan B, et al. Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. In: 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, 2010. 152--153&
[50]
Ghani T, Armstrong M, Auth C, et al. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2003. 11.6.1--11.6.3.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Ghani T, Armstrong M, Auth C, et al. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2003. 11.6.1--11.6.3&
[51]
Lee W-H, Waite A, Nii H, et al. High performance 32nm SOI CMOS with high-k/metal gate and 0.149$\upmu $m$^{2}$ SRAM and ultra low-k back end with eleven levels of copper. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2005. 56--59.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Lee W-H, Waite A, Nii H, et al. High performance 32nm SOI CMOS with high-k/metal gate and 0.149$\upmu $m$^{2}$ SRAM and ultra low-k back end with eleven levels of copper. In: Technical Digest of International Electron Devices Meeting, Washington DC, 2005. 56--59&
[52]
Narasimha S, Chang P, Ortolland C, et al. 22nm high-performance SOI technology featuring dual-embedded stressors, epi-plate high-k deep-trench embedded DRAM and self-aligned via 15LM BEOL. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2012. 3.3.1--3.3.4.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Narasimha S, Chang P, Ortolland C, et al. 22nm high-performance SOI technology featuring dual-embedded stressors, epi-plate high-k deep-trench embedded DRAM and self-aligned via 15LM BEOL. In: Technical Digest of International Electron Devices Meeting, San Francisco, 2012. 3.3.1--3.3.4&
[53]
Leobandung E, Nayakama H, Mocuta D, et al. High performance 65 nm SOI technology with dual stress line and low capacitance SRAM cell. In: 2005 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, 2005. 126--127.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Leobandung E, Nayakama H, Mocuta D, et al. High performance 65 nm SOI technology with dual stress line and low capacitance SRAM cell. In: 2005 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, 2005. 126--127&
[54]
Ota K, Sugihara K, Sayama H, et al. Novel locally strained channel technique for high performance 55 nm CMOS. In: Proceedings of International Electron Devices Meeting, San Francisco, 2002, 27--30.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Ota K, Sugihara K, Sayama H, et al. Novel locally strained channel technique for high performance 55 nm CMOS. In: Proceedings of International Electron Devices Meeting, San Francisco, 2002, 27--30&
[55]
Lim K-Y, Lee H, Ryu C, et al. Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices. In: Proceedings of International Electron Devices Meeting, San Francisco, 2010. 10.1.1--10.1.4.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Lim K-Y, Lee H, Ryu C, et al. Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices. In: Proceedings of International Electron Devices Meeting, San Francisco, 2010. 10.1.1--10.1.4&
[56]
Jan C-H, Bhattacharya U, Brain R, et al. A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications. In: Proceedings of International Electron Devices Meeting, San Francisco, 2012. 3.1.1--3.1.4.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Jan C-H, Bhattacharya U, Brain R, et al. A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications. In: Proceedings of International Electron Devices Meeting, San Francisco, 2012. 3.1.1--3.1.4&
[57]
Natarajan S, Agostinelli M, Akbar S, et al. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588$\upmu$m$^2$ SRAM cell size. In: Proceedings of International Electron Devices Meeting, San Francisco, 2014. 3.7.1--3.7.3.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Natarajan S, Agostinelli M, Akbar S, et al. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588$\upmu$m$^2$ SRAM cell size. In: Proceedings of International Electron Devices Meeting, San Francisco, 2014. 3.7.1--3.7.3&
[58]
Jan C-H, Al-amoody F, Chang H-Y, et al. A 14 nm SoC platform technology featuring 2nd generation tri-gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um$^{2}$ SRAM cells, optimized for low power, high performance and high density SoC products. In: Proceedings of 2015 Symposium on VLSI Technology, Kyoto, 2015. T12--T13.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Jan C-H, Al-amoody F, Chang H-Y, et al. A 14 nm SoC platform technology featuring 2nd generation tri-gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um$^{2}$ SRAM cells, optimized for low power, high performance and high density SoC products. In: Proceedings of 2015 Symposium on VLSI Technology, Kyoto, 2015. T12--T13&
[59]
Liu Q, DeSalvo B, Morin P, et al. FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node. In: Proceedings of International Electron Devices Meeting, San Francisco, 2014. 9.1.1---9.1.4.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Liu Q, DeSalvo B, Morin P, et al. FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node. In: Proceedings of International Electron Devices Meeting, San Francisco, 2014. 9.1.1---9.1.4&
[60]
Kube M, Hori R, Minato O, et al. A threshold voltage controlling circuit for short channel MOS integrated circuits. In: Technical Digest of 1976 IEEE International Solid-State Circuits Conference, Philadelphia, 1976. 54--55.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Kube M, Hori R, Minato O, et al. A threshold voltage controlling circuit for short channel MOS integrated circuits. In: Technical Digest of 1976 IEEE International Solid-State Circuits Conference, Philadelphia, 1976. 54--55&
[61]
Thompson S, Young I, Greason J, et al. Dual threshold voltage and substrate bias: Keys to high performance, low power, 0.1 $\upmu $m logic designs. In: 1997 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, 1997. 69--70.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Thompson S, Young I, Greason J, et al. Dual threshold voltage and substrate bias: Keys to high performance, low power, 0.1 $\upmu $m logic designs. In: 1997 Symposium on VLSI Technology, Digest of Technical Papers, Kyoto, 1997. 69--70&
[62]
Nomura S, Tachibana F, Fujita T, et al. A 9.7mW AAC-decoding, 620mW H.264 720p 60fps decoding, 8-core media processor with embedded forward-body-biasing and power-gating circuit in 65nm CMOS technology. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, 2008. 262--612.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Nomura S, Tachibana F, Fujita T, et al. A 9.7mW AAC-decoding, 620mW H.264 720p 60fps decoding, 8-core media processor with embedded forward-body-biasing and power-gating circuit in 65nm CMOS technology. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, 2008. 262--612&
[63]
Sumita
M,
Sakiyama
S,
Kinoshita
M, et al.
IEEE J Solid-State Circuits,
2005, 40: 60-66
Google Scholar
http://scholar.google.com/scholar_lookup?author=Sumita M&author=Sakiyama S&author=Kinoshita M&publication_year=2005&journal=IEEE J Solid-State Circuits&volume=40&pages=60-66
[64]
Jacquet
D,
Hasbani
F,
Flatresse
P, et al.
IEEE J Solid-State Circuits,
2014, 49: 812-826
Google Scholar
http://scholar.google.com/scholar_lookup?author=Jacquet D&author=Hasbani F&author=Flatresse P&publication_year=2014&journal=IEEE J Solid-State Circuits&volume=49&pages=812-826
[65]
Wilson R, Beigne E, Flatresse P, et al. A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, Embedding FMAX Tracking. In: 2014 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, 2014. 452--453.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Wilson R, Beigne E, Flatresse P, et al. A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, Embedding FMAX Tracking. In: 2014 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, 2014. 452--453&
[66]
Ishibashi K, Sugii N, Usami K, et al. A perpetuum mobile 32bit CPU with 13.4pJ/cycle, 0.14$\upmu $A sleep current using reverse body bias assisted 65nm SOTB CMOS technology. In: 2014 IEEE COOL Chips XVII, Yokohama, 2014. 1--3.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Ishibashi K, Sugii N, Usami K, et al. A perpetuum mobile 32bit CPU with 13.4pJ/cycle, 0.14$\upmu $A sleep current using reverse body bias assisted 65nm SOTB CMOS technology. In: 2014 IEEE COOL Chips XVII, Yokohama, 2014. 1--3&
[67]
Beigne
E,
Valentian
A,
Miro-Panades
I, et al.
6GHz at 1.3V,
32 bits VLIW DSP embedding $F_{max}$ tracking. {IEEE J Solid-State Circuits}, 2015, 50: 125-136
Google Scholar
http://scholar.google.com/scholar_lookup?author=Beigne E&author=Valentian A&author=Miro-Panades I&publication_year=32 bits VLIW DSP embedding $F_{max}$ tracking. {IEEE J Solid-State Circuits}&journal=6GHz at 1.3V&volume=2015, 50&pages=125-136
[68]
Clerc S, Saligane M, Abouzeid F, et al. A 0.33V/$-40^\circ\text{C}$ process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. In: Proceedings of 2015 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2015. 1--3.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Clerc S, Saligane M, Abouzeid F, et al. A 0.33V/$-40^\circ\text{C}$ process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. In: Proceedings of 2015 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 2015. 1--3&
[69]
SFARDS. SFARDS new 28nm BTC & LTC dual-algorithm ASIC unveiled. http://www.sfards.com/detail?id=26.
Google Scholar
http://scholar.google.com/scholar_lookup?title=SFARDS. SFARDS new 28nm BTC & LTC dual-algorithm ASIC unveiled. http://www.sfards.com/detail?id=26&
[70]
Bitcoin Wiki. ASIC. https://en.bitcoin.it/wiki/ASIC.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Bitcoin Wiki. ASIC. https://en.bitcoin.it/wiki/ASIC&
[71]
Miyazaki M, Kao J, Chandrakasan A P. A 175mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture. In: 2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, 2002.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Miyazaki M, Kao J, Chandrakasan A P. A 175mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture. In: 2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, 2002&
[72]
Keshavarizi
A,
Narendra
S,
Bloechel
B, et al.
IEEE J Solid-State Circuits,
2003, 38: 696-701
Google Scholar
http://scholar.google.com/scholar_lookup?author=Keshavarizi A&author=Narendra S&author=Bloechel B&publication_year=2003&journal=IEEE J Solid-State Circuits&volume=38&pages=696-701
[73]
Soitec. Press release ``Soitec and Shin-Etsu Handotai announce Smart Cut{\texttrademark} licensing extension and expanded technology cooperation". 2012. http://www.soitec.com/en/news/press-releases/soitec-and-shin-etsu-handotai-announce-smart-cut-licensing-extension-and-expanded-technology-cooperation-1079/.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Soitec. Press release ``Soitec and Shin-Etsu Handotai announce Smart Cut{\texttrademark} licensing extension and expanded technology cooperation". 2012. http://www.soitec.com/en/news/press-releases/soitec-and-shin-etsu-handotai-announce-smart-cut-licensing-extension-and-expanded-technology-cooperation-1079/&
[74]
Shin-Etsu
Handotai Co.
Ultra Thin Body and Buried oxide substrate supply chain. FD-SOI Workshop,
Kyoto, 2013. http: ://-{\
Google Scholar
http://scholar.google.com/scholar_lookup?author=Shin-Etsu Handotai Co&publication_year=Kyoto&journal=Ultra Thin Body and Buried oxide substrate supply chain. FD-SOI Workshop&volume=2013. http&pages=://-{\
[75]
Soitec. Press release ``Soitec and SunEdison enter into patent license agreement". 2013. http://www.soitec.com/en-\linebreak /news/press-releases/soitec-and-sunedison-enter-into-patent-license-agreement-1390/.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Soitec. Press release ``Soitec and SunEdison enter into patent license agreement". 2013. http://www.soitec.com/en-\linebreak /news/press-releases/soitec-and-sunedison-enter-into-patent-license-agreement-1390/&
[76]
Seo K-I, Haran B, Gupta D, et al. A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI. In: 2014 Symposium on VLSI Technology: Digest of Technical Papers, Honolulu, 2014. 1--2.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Seo K-I, Haran B, Gupta D, et al. A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI. In: 2014 Symposium on VLSI Technology: Digest of Technical Papers, Honolulu, 2014. 1--2&
[77]
Seo S-C, Edge L F, Kanakasabapathy S, et al. Full metal gate with borderless contact for 14 nm and beyond. In: Proceedings of 2011 Symposium on VLSI Technology (VLSIT), Honolulu, 2011. 36--37.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Seo S-C, Edge L F, Kanakasabapathy S, et al. Full metal gate with borderless contact for 14 nm and beyond. In: Proceedings of 2011 Symposium on VLSI Technology (VLSIT), Honolulu, 2011. 36--37&
[78]
Kamohara S, Sugii N, Yamamoto Y, et al. Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era. In: 2014 Symposium on VLSI Technology: Digest of Technical Papers, Honolulu, 2014. 1--2.
Google Scholar
http://scholar.google.com/scholar_lookup?title=Kamohara S, Sugii N, Yamamoto Y, et al. Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era. In: 2014 Symposium on VLSI Technology: Digest of Technical Papers, Honolulu, 2014. 1--2&