SCIENCE CHINA Information Sciences, Volume 60 , Issue 12 : 129401(2017) https://doi.org/10.1007/s11432-016-0711-y

A four-channel time-interleaved 30-GS/s 6-bit ADC in 0.18 $\mu$m SiGe BiCMOS technology

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  • ReceivedOct 29, 2016
  • AcceptedDec 12, 2016
  • PublishedFeb 24, 2017


There is no abstract available for this article.


This work was supported in part by National High Technology Research and Development Program of China (863 Program) (Grant No. 2013AA011201) and Wuhan Research Institute of Posts and Telecommunications (WRI). We would like to thank Dr. Jiang Fan from WRI for his technical support.


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  • Figure 1

    The overall architecture and measured results of the proposed ADC. (a) The overall architecture of the proposed ADC; (b) SFDR and ENOB versus input frequency.