SCIENCE CHINA Information Sciences, Volume 59 , Issue 4 : 042403(2016) https://doi.org/10.1007/s11432-015-5381-z

Dynamically reconfigurable architecture for symmetric ciphers

More info
  • ReceivedApr 2, 2015
  • AcceptedMay 8, 2015
  • PublishedMar 1, 2016




This work was supported by the project from State Grid Cooperation of China (Grant No. SGRIDGKJ[2013]548).


[1] Stallings W. Network and Internetwork Security: Principles and Practice. Upper Saddle River: Prentice Hall, 2010. Google Scholar

[2] Hiertz G R, Denteneer D, Stibor L, et al. The IEEE 802. 11 Universe. IEEE Commun Mag, 2010, 4862-70 Google Scholar

[3] LAN/MAN Standards Committee. IEEE Std 802.3-2008. 2008. Google Scholar

[4] O'Melia S, Elbirt A J. Enhancing the performance of symmetric-key cryptography via instruction set extensions. IEEE Trans Very Large Scale Integr Syst, 2010, 181505-1518 CrossRef Google Scholar

[5] Bossuet L, Grand M, Gaspar L, et al. Architectures of flexible symmetric key crypto engines: a survey from hardware coprocessor to multi-crypto-processor system on chip. ACM Comput Surv, 2013, 4541-1518 Google Scholar

[6] Granado-Criado J M, Vega-Rodrguez M A, Snchez-Prez J M, et al. A new methodology to implement the AES algorithm using partial and dynamic reconfiguration. Integration, 2010, 4372-80 Google Scholar

[7] Taherkhani S, Ever E, Gemikonakli O. Implementation of non-pipelined and pipelined data encryption standard (DES) using Xilinx Virtex-6 FPGA technology. In: Proceedings of IEEE 10th International Conference on Computer and Information Technology (CIT), Bradford, 2010. 1257--1262. Google Scholar

[8] Wang L, Jing J W, Liu Z B, et al. Evaluating optimized implementations of stream cipher ZUC algorithm on FPGA. In: Proceedings of 13th International Conference on Information and Communications Security, Beijing, 2011. 202--215. Google Scholar

[9] Venugopal V, Shila D M. High throughput implementations of cryptography algorithms on GPU and FPGA. In: Proceedings of IEEE International Instrumentation and Measurement Technology Conference, Minneapolis, 2013. 723--727. Google Scholar

[10] Bulens P, Standaert F, Quisquater J, et al. Implementation of the AES-128 on Virtex-5 FPGAs. In: Proceedings of 1st International Conference on Cryptology in Africa, Casablanca, 2008. 16--26. Google Scholar

[11] Standaert F X, Piret G, Rouvroy G, et al. FPGA implementations of the ICEBERG block cipher. Integration, 2007, 4020-27 Google Scholar

[12] Yang H, Basutkar N, Xue P, et al. Software-defined DVT-T2 demodulator using scalable DSP processors. IEEE Trans Consum Electron, 2013, 59428-434 CrossRef Google Scholar

[13] Garcia A, Berekovic M, Aa T V. Mapping of the AES cryptographic algorithm on a coarse-grain reconfigurable array processor. In: Proceedings of International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Leuven, 2008. 245--250. Google Scholar

[14] Rossi D, Mucci C, Campi F, et al. Application space exploration of a heterogeneous run-time configurable digital signal processor. IEEE Trans Very Large Scale Integr Syst, 2013, 21193-205 CrossRef Google Scholar

[15] PACT, X. XPP-III processor overview. White Paper Version. 2006. Google Scholar

[16] Majzoub S, Diab H. MorphoSys reconfigurable hardware for cryptography: the twofish case. J Supercomput, 2012, 5922-41 CrossRef Google Scholar

[17] Mucci C, Vanzolini L, Campi F, et al. Interactive presentation: implementation of AES/Rijndael on a dynamically reconfigurable architecture. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE), EDA Consortium, 2007. 355--360. Google Scholar

[18] Elbirt A J, Paar C. An instruction-level distributed processor for symmetric-key cryptography. IEEE Trans Parall Distr Syst, 2005, 16468-480 CrossRef Google Scholar

[19] Cong J, Xiao B J. MrFPGA: a novel FPGA architecture with memristor-based reconfiguration. In: Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), San Diego, 2011. 1--8. Google Scholar

[20] NIST. Advanced encryption standard (AES). 2001. http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf. Google Scholar

[21] NIST-FIPS. Data Encryption Standard. Federal Information Processing Standards (FIPS) Publication. 1999. http://csrc.nist.gov/encryption/tkencryption.html. Google Scholar

[22] Handsehuh H, Naccache D S. SHACAL. In: Proceedings of 1st Open NESSIE Workshop, 2000. 13--14. http://www.\linebreak oscca.gov.cn/UpFile/200621016423197990.pdf. Google Scholar

[23] OSCCA (Office of State Commercial Cryptography Administration, China). The SMS4 Block Cipher. 2006. http://www.oscca.gov.cn/UpFile/200621016423197990.pdf. Google Scholar

[24] ETSI/SAGE Specification. Specification of the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3. Document 2: ZUC Specification. Version 1.5. 2011. Google Scholar

[25] Todman T J, Constantinides G A, Wilton S J, et al. Reconfigurable Computing: architectures and design methods. IEE Proc-Comput Dig Tech, 2005, 152193-207 CrossRef Google Scholar

[26] Xilinx. Virtex-5 FPGA User Guide. 2009. Google Scholar

[27] Gentry C, Halevi S, Smart N P. Fully homomorphic encryption with polylog overhead. In: Proceedings of 31st Annual International Conference on the Theory and Applications of Cryptographic Techniques, Cambridge, 2012. 465--482. Google Scholar

[28] Lambrechts A, Raghavan P, Jayapala M, et al. Interconnect exploration for energy versus performance tradeoffs for coarse grained reconfigurable architectures. IEEE Trans Very Large Scale Integr Syst, 2009, 17151-155 CrossRef Google Scholar

[29] PACT. White Paper of Video Decoding on XPP-III. 2006. Google Scholar

[30] Liu B, Baas B M. Parallel AES encryption engines for many-core processor arrays. IEEE Trans Comput, 2013, 3536-547 Google Scholar

[31] Xilinx. XPower Estimator User Guide. 2012. Google Scholar


Contact and support