SCIENCE CHINA Information Sciences, Volume 59 , Issue 8 : 082401(2016) https://doi.org/10.1007/s11432-015-0471-4

A yield-enhanced global optimization methodology for analog circuit based on extreme value theory

More info
  • ReceivedDec 24, 2015
  • AcceptedFeb 16, 2016
  • PublishedJun 7, 2016



National Natural Science Foundation of China(1115556)

National Natural Science Foundation of China(61574044)

National Natural Science Foundation of China(61125401)

National Natural Science Foundation of China(61376040)

National Natural Science Foundation of China(61574046)

Recruitment Program of Global Experts(the Thous)

Recruitment Program of Global Experts(Talents Plan)



This work was supported by National Natural Science Foundation of China (Grant Nos. 1115556, 61574044, 61125401, 61376040, 61574046), Recruitment Program of Global Experts (the Thousand Talents Plan) and Fudan University ASIC & Systems State Key Lab.


[1] Naviasky E, Nizic M. Mixed-signal design challenges and requirements. http://www.cadence.com/rl/Resources/ white\_papers/mixed\_signal\_challenges\_wp.pdf. Google Scholar

[2] Jafari A, Zekri M, Sadri S, et al. Design of analog integrated circuits by using genetic algorithm. In: Proceedings of the 2nd International Conference on Computer Engineering and Applications (ICCEA), Bali Island, 2010. 1: 578--581. Google Scholar

[3] Sabat S L, Kumar K S, Udgata S K. Differential evolution and swarm intelligence techniques for analog circuit synthesis. In: Proceedings of World Congress on Nature & Biologically Inspired Computing, Coimbatore, 2009. 469--474. Google Scholar

[4] Razzaghpour M, Rusu A. Analog circuit optimization via a modified imperialist competitive algorithm. In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, 2011. 2273--2276. Google Scholar

[5] Kotti M, Benhala B, Fakhfakh M, et al. Comparison between PSO and ACO techniques for analog circuit performance optimization. In: Proceedings of International Conference on Microelectronics (ICM), Hammamet, 2011. 1--6. Google Scholar

[6] Yuan J, Farhat N, van der Spiegel J. GBOPCAD: a synthesis tool for high-performance gain-boosted opamp design. IEEE Trans Circ Syst I: Regular Papers, 2007, 521535-1544 Google Scholar

[7] Rutenbar R A. Simulated annealing algorithms: an overview. IEEE Circ Device Mag, 1989, 519-26 CrossRef Google Scholar

[8] Barros M, Guilherme J, Horta N. Analog circuits optimization based on evolutionary computation techniques. Integr VLSI J, 2010, 43136-155 CrossRef Google Scholar

[9] Schenkel F, Pronath M, Zizala S, et al. Mismatch analysis and direct yield optimization by specwise linearization and feasibility-guided search. In: Proceedings of the 38th Annual Design Automation Conference. New York: ACM, 2001. 858--863. Google Scholar

[10] Schwencker R, Schenkel F, Pronath M, et al. Analog circuit sizing using adaptive worst-case parameter sets. In: Proceedings of Design, Automation and Test in Europe Conference and Exhibition, Paris, 2002. 581--585. Google Scholar

[11] Pehl M, Zwerger M, Graeb H. Variability-aware automated sizing of analog circuits considering discrete design parameters. In: Proceedings of the 13th International Symposium on Integrated Circuits (ISIC), Singapore, 2011. 12--14. Google Scholar

[12] Wang Z, Director S. An efficient yield optimization method using a two-step linear approximation of circuit performance. In: Proceedings of IEEE European Design and Test Conference, Paris, 1994. 567--571. Google Scholar

[13] Liu B, Fernandez F V, Gielen G E. Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques. IEEE Trans Comput Aided Design Integr Circ Syst, 2011, 30793-805 CrossRef Google Scholar

[14] McConaghy T, Gielen G. Globally reliable variation-aware sizing of analog integrated circuits via response surfaces and structural homotopy. IEEE Trans Comput Aided Design, 2009, 281627-1640 CrossRef Google Scholar

[15] Afacan E, Berkol G, Pusane A E, et al. Adaptive sized quasi-Monte Carlo based yield aware analog circuit optimization tool. In: Proceedings of the 5th European Workshop on CMOS Variability (VARI), Palma de Mallorca, 2014. 1--6. Google Scholar

[16] Debyser G, Gielen G. Efficient analog circuit synthesis with simultaneous yield and robustness optimization. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design. New York: ACM, 1998. 308--311. Google Scholar

[17] Mukherjee T, Carley L, Rutenbar R. Efficient handling of operating range and manufacturing line variations in analog cell synthesis. IEEE Trans Comput Aided Design Integr Circ Syst, 2000, 19825-839 CrossRef Google Scholar

[18] Dharchoudhury A, Kang S. Worst-case analysis and optimization of VLSI circuit performances. IEEE Trans Comput Aided Design Integr Circ Syst, 1995, 14481-492 CrossRef Google Scholar

[19] Li X, Gopalakrishnan P, Xu Y, et al. Robust analog/RF circuit design with projection-based performance modeling. IEEE Trans Comput Aided Design Integr Circ Syst, 2007, 262-15 CrossRef Google Scholar

[20] Director S, Feldmann P, Krishna K. Statistical integrated circuit design. IEEE J Solid-State Circ, 1993, 28193-202 CrossRef Google Scholar

[21] Antreich K, Graeb H, Wieser C. Circuit analysis and optimization driven by worst-case distances. IEEE Trans Comput Aided Design Integr Circ Syst, 1994, 1357-71 CrossRef Google Scholar

[22] Qian L X, Zhou D, Wang S G, et al. Worst case analysis of linear analog circuit performance based on Kharitonov's rectangle. In: Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Shanghai, 2010. 800--802. Google Scholar

[23] Hao Z, Tan X D, Shen R, et al. Performance bound analysis of analog circuits considering process variations. In: Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference (DAC). New York: ACM, 2011. 310--315. Google Scholar

[24] Liu X, Palma-Rodriguez A A, Rodriguez-Chavez S, et al. Performance bound and yield analysis for analog circuits under process variations. In: Proceedings of 18th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, 2013. 761--766. Google Scholar

[25] Kuo P, Saibua S, Huang G, et al. An efficient method for evaluating analog circuit performance bounds under process variations. IEEE Trans Circ Syst-II, 2012, 59351-355 CrossRef Google Scholar

[26] Huang G, Qian L, Saibua S, et al. An efficient optimization based method to evaluate the DRV of SRAM cells. IEEE Trans Circ Syst I, 2013, 601511-1520 Google Scholar

[27] Tiwary S K, Tiwary P K, Rutenbar R A. Generation of yield aware Pareto surfaces for hierarchical circuit design space exploration. In: Proceedings of the 43rd annual Design Automation Conference. New York: ACM, 2006. 31--36. Google Scholar

[28] Singhee A, Rutenbar R A. Why quasi-Monte Carlo is better than Monte Carlo or latin hypercube sampling for statistical circuit analysis. IEEE Trans Comput Aided Design Integr Circ Syst, 2010, 291763-1776 CrossRef Google Scholar

[29] Wikipedia. Newton's method. http://en.wikipedia.org/wiki/Newton's\_method. Google Scholar

[30] Schittkowski K. NLPQLP: a new Fortran implementation of a sequential quadratic programming algorithm for parallel computing. http://tomopt.com/docs/nlpqlp.pdf. Google Scholar

[31] Stoer J. Foundations of recursive quadratic programming methods for solving nonlinear programs. In: Computational Mathematical Programming. Berlin: Springer, 1985. 15. Google Scholar

[32] Nocedal J, Wright S J. Numerical Optimization. 2nd ed. Berlin: Springer, 2006. Google Scholar

[33] Graeb H. Analog Design Centering and Sizing. Berlin: Springer, 2007. Google Scholar

[34] Afacan E, Berkol G, Baskaya F, et al. Sensitivity based methodologies for process variation aware analog IC optimization. In: Proceedings of the 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Grenoble, 2014. 1--4. Google Scholar

[35] Afacan E, Berkol G, Pusane A E, et al. Adaptive sized quasi-Monte Carlo based yield aware analog circuit optimization tool. In: Proceedings of the 5th European Workshop on CMOS Variability (VARI), Palma de Mallorca, 2014. 1--6. Google Scholar

[36] Kotz S, Nadarajah S. Extreme Value Distributions: Theory and Applications. London: Imperial College Press, 2000. Google Scholar

[37] The Mathworks Inc. Generalized Extreme Value Distribution. http://www.mathworks.com/help/stats/generalized-extreme-value-distribution.html. Google Scholar

[38] Evmorfopoulos N E, Stamoulis G I, Avaritsiotis J N. A Monte Carlo approach for maximum power estimation based on extreme value theory. IEEE Trans CAD, 2002, 214-1776 Google Scholar

[39] Sheppard M. Fit all valid parametric probability distributions to data. http://www.mathworks.com/matlabcentral/ fileexchange/34943-fit-all-valid-parametric-probability-distributions-to-data/content/allfitdist.m. Google Scholar


Contact and support